Semiconductor nanowires (NWs) and carbon nanotubes represent promising building blocks for the bottom-up assembly of integrated electronic and photonic systems because these materials can exhibit diverse device behavior and simultaneously function as the 'wires' that access and interconnect devices.^1-3 Efforts to date have focused primarily on the demonstration of individual nanodevices including field effect transistors,^4-7 diodes,^8,9 light-emitting diodes,^6,9,10 and diode lasers.¹¹ Yet to move forward and possibly go beyond existing technologies will require the development of approaches that enable controlled assembly and integration of these building blocks on a scale far beyond that of individual or small numbers of devices produced by fluidic¹² and electric-field¹³ directed assembly.

Here we report a solution-based approach for hierarchically organizing NW building blocks en masse into integrated arrays tiled over large areas. NWs were aligned with controlled nanometer to micrometer scale pitch using the Langmuir-Blodgett technique, transferred to planar substrates in a layer-by-layer process to form parallel and crossed NW structures over centimeter length scales, and then efficiently patterned into repeating arrays of controlled dimensions and pitch using photolithography. This solution-based method enables the specific NW building block, NW pitch, NW orientation, array size, array orientation, and array pitch to be controlled independently for sequential depositions, and thus offers a flexible pathway for bottom-up assembly of NW and nanotube materials into integrated and hierarchically organized structures.

Our approach for controlled assembly of NWs (Figure 1) exploits the Langmuir-Blodgett (LB) technique¹⁴ to uniaxially compress a NW-surfactant monolayer on an aqueous subphase, thereby producing aligned NWs with controlled spacing. The compressed layer is then transferred in a single step to a planar substrate to yield parallel NWs covering the entire substrate surface. In addition, this sequence of steps can be repeated one or more times with controlled orientation to produce crossed and more complex NW structures, where the NWs can be the same or different in sequential layers. The ability to assemble a wide range of different NW building blocks in a flexible manner is a unique attribute of this bottom-up approach and quite distinct from top-down fabrication methods. The Langmuir-Blodgett technique was used previously to organize single layers of low aspect ratio nanorods into close-packed structures suggestive of liquid crystalline phases,¹⁵ although this latter work did not demonstrate control of spacing and other properties critical to integrated and interconnected arrays. In addition, we have recently used this method to prepare large area NW masks for deposition and etching.¹⁶

Figure 1 NWs (blue lines) in a monolayer of surfactant at the air-water interface are (a) compressed on a Langmuir-Blodgett trough to a specified pitch. (b) The aligned NWs are transferred to the surface of a substrate to make a uniform parallel array. (c) Crossed NW structures are formed by uniform transfer of a second layer of aligned parallel NWs (red lines) perpendicular to the first layer (blue lines).

We illustrate the flexibility of our approach using silicon NWs that were prepared with nearly monodisperse diameters by nanocluster catalyzed chemical vapor deposition.¹⁷ Stable NW suspensions in nonpolar solvents made using the surfactant 1-octadecylamine, which coordinates reversibly to NW surfaces, were spread on the surface of the aqueous phase in a Langmuir-Blodgett trough and compressed.¹⁸ During compression, NWs become aligned along their long axes with the average spacing (center-to-center distance) controlled by the compression process. Large area field-emission scanning electron microscopy images (Figure 2A) show that parallel NWs were transferred with good uniformity and alignment onto substrates with areas up to 20 cm² in our experiments, although this approach can be applied to much larger area substrates.¹⁹

Figure 2 (A) Large area image of parallel NWs deposited uniformly on a 1 cm × 3 cm substrate. Scale bar, 100 m. (B, C), Images of aligned parallel NWs transferred to substrates at different stages of LB compression. The scale bars in (B, C) correspond to 1 m. (D, E) Images of high-density parallel NW arrays with average pitches of (D) ~90 and (E) ~45 nm; NWs with core diameters of 70 and 25 nm, respectively, and 10 nm silicon oxide shell thicknesses were used for assembly. The scale bars in (D, E) correspond to 200 nm. Images were recorded with a field-emission scanning electron microscope.

Significantly, we are also able to control the spacing of the transferred NWs from the micrometer scale to well-ordered and close-packed structures by the compression process. Representative images of transferred NWs with spacings of ca. 0.8 and 0.4 m (Figures 2B, 2C) show that the NWs are isolated and have good uniaxial alignment. In general, we find that the transferred NW arrays have similar quality for spacings from ca. 2 m (the largest studied) to 200 nm. Compression to spacings below ca. 200 nm leads to increasing aggregation due to strong inter-NW attractive forces, although aligned close-packed monolayer structures can be transferred. This latter capability was used to make ultrahigh-density arrays with the NW spacing controlled on the nanometer scale, by compressing NWs coated with controlled thickness sacrificial layers, and then removing this layer once transferred.¹⁶ For example, core/shell Si/SiO₂ NWs, in which the oxide shell thickness was precisely controlled during NW growth,²⁰ were compressed to close-packed structures and transferred to substrates. Images recorded following HF etching of the oxide shells show well aligned parallel NWs with center-to-center separations of 90 nm (Figure 2D) and ca. 45 nm (Figure 2E) that are in agreement with the values predicted based on the dimensions of the core/shell NWs; that is, the center-to-center separation is equal to 2 × (NW radius + shell thickness). We have also used selective dry (i.e., reactive ion) etching to remove oxide from core/shell Si/SiO₂ NWs to produce similar structures.¹⁶ In addition, it should be possible to extend this approach to even finer spacings that would be difficult to achieve by top-down lithography.

The aligned, controlled spacing NW structures exhibit features similar to a nematic liquid crystal phase, including fluctuations in the average alignment direction and poor end-to-end registry (Figure 2C). These nonuniform features are distinct from the precise structures familiar to conventional top down fabrication; however, we do not believe these features represent serious impediments to making integrated and interconnected devices. Specifically, interconnected finite-size arrays of nanoscale devices are more desirable than monolithic structures for integrated nanosystems, because hierarchical organization reduces the probability that small numbers of defects will cause catastrophic failure in the whole system.²¹ Hence, by adjusting this array size to be less than the average NW length it is possible to minimize the number of NWs that fail to span the width of an array due to poor end-to-end registry.

We have implemented this desired hierarchical patterning of the transferred NW structures in a flexible and scalable manner using photolithography (Figure 3). Following uniform transfer of NWs of a specified spacing onto a substrate, photolithography is used to define a pattern over the entire substrate surface, which sets the array dimensions and array pitch, and then the NWs outside the patterned array are removed by gentle sonication.^16,22 An image of a 10 m × 10 m square array with a 25 m array pitch (Figure 3B) shows that this method provides ready and scalable access to ordered arrays over large areas. This array exhibits order on multiple length scales - 40 nm diameter NWs, 0.5 m NW spacing, 10 m array size, 25 m array pitch repeated over centimeters - that is representative of the substantial control enabled by our approach. In addition, this approach can be used to define array geometries and tiling patterns more complex than the above square structures.

Figure 3 (A) Hierarchical patterning of parallel NW arrays by lithography, where NWs are removed from regions outside of the defined array pattern. (B) Image of patterned 10 m × 10 m parallel NW arrays. Scale bar, 25 m. (inset) Large area dark-field optical micrograph of patterned parallel NW arrays. The inset scale bar is 100 m. (C) Typical linear current vs voltage curves recorded from three NW devices. The resistance varies from 260 to 1780 k for the blue, green, and red curves, respectively. Inset shows representative scanning electron microscopy image of four aligned NW devices defined by electron beam lithography; the scale bar is 3 m.

We have also investigated whether our new approach for assembling and patterning hierarchical NW arrays is compatible with fabrication of nanoelectronic devices. To test this important point, electron beam lithography was used to define a series of parallel finger electrodes contacting NWs in hierarchically patterned parallel arrays (Figure 3C). Electrical transport measurements carried out on three of the silicon NW devices exhibit linear current versus voltage behavior. This linear response and the typical two-terminal resistance values, 260-1780 k, are indicative of good electrical contacts. We believe these preliminary results are important because they demonstrate that our solution-based hierarchical assembly methodology produces electrically active NWs, and therefore should be compatible with the goal of creating large-scale integrated, functional nanosystems. Significantly, recent studies using a scalable photolithography approach provide clear demonstration of this milestone.²³

Last, our method can be used to make crossed NW arrays by transferring sequential layers of aligned NWs in an orthogonal orientation and then patterning the layers as described above (Figure 4A).²² Crossed arrays are particularly attractive targets because previous small scale studies of crossed NW junctions have demonstrated interesting electronic⁷ and photonic⁶ function. Large area images of two silicon NW layers transferred sequentially with orthogonal alignment (Figure 4B) show that this approach yields relatively uniform coverage over centimeter length scales. Images of crossed NW arrays (Figure 4C), which were made by defining an array pattern with photolithography and then removing NWs outside of the patterned areas, show that regular 10 m × 10 m square arrays with a 25 m array pitch can be achieved over large areas and that each of the square arrays consists of a large number of crossed NW junctions. In addition, we have made ultrahigh-density crossed NW arrays using the method described above. Close-packed Si/SiO₂ core/shell NWs were transferred in two orthogonal layers and then etched with HF to yield crossed NW arrays with pitches of less than 50 nm (Figure 4D). Because good electrical contacts to NW arrays assembled and patterned by our approach have been realized (Figure 3C), we believe it will be possible to create integrated nanosystems with diverse functions using these hierarchical crossed NW arrays in the future.

Figure 4 (A) Hierarchical patterning of crossed NW arrays by lithography, where NWs are removed from regions outside of the defined array pattern. (B) Dark-field optical micrograph of crossed NWs deposited uniformly on a 1 cm × 1 cm substrate; scale bar is 50 m. (C) Scanning electron microscopy image of patterned crossed NW arrays; scale bar, 10 m. (inset) Large area dark-field optical micrograph of the patterned crossed NW arrays; scale bar is 100 m. (D) Scanning electron microscopy image of an ultrahigh-density crossed NW array; scale bar is 200 nm.

In summary, our studies have outlined a general and rational strategy for hierarchical organization of NWs and represent substantial progress toward the bottom-up assembly of integrated architectures over large areas in a highly parallel and scalable manner. The facile substitution of different NWs and changes in structural hierarchy enabled by this approach will be attractive for creating integrated, functional nanosystems. For example, crossed NW arrays could be used as addressable nanoscale light-emitting diode sources. More generally, efforts focused on increasing the structural complexity, for example by tiling functionally distinct arrays using additional transfer steps, could enable combinations of logic and memory arrays that are needed for nanocomputing²¹ or even integrated sensing and processing function.

Acknowledgment

We acknowledge A. DeHon, Y. Cui, D. Wang, Z. Zhong, S. I. Yang, and K. Hata for useful discussion, and thank G. Zheng and L. Lauhon for supplying Si/SiO₂ core/shell NWs. D.W. thanks the Korea Science and Engineering Foundation (KOSEF) for postdoctoral fellowship support, and C.M.L. acknowledges support from the Defense Advanced Projects Research Agency.

Note Added after ASAP. Reference citations in the text have been corrected. This paper was originally posted ASAP on 8/5/03. The corrected version was posted on 8/14/03.