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Letter

Sub-10 nm Carbon Nanotube Transistor

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Aaron D. Franklin*†, Mathieu Luisier‡, Shu-Jen Han†, George Tulevski†, Chris M. Breslin†, Lynne Gignac†, Mark S. Lundstrom§, and Wilfried Haensch†

^† IBM T. J. Watson Research Center, Yorktown Heights, New York 10598, United States

^‡ Integrated Systems Laboratory, ETH Zurich, 8092 Zurich, Switzerland

^§ School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907, United States

Nano Lett., 2012, 12 (2), pp 758–762

DOI: 10.1021/nl203701g

Publication Date (Web): January 18, 2012

*E-mail: aaronf@us.ibm.com.

Section:

Electric Phenomena

Abstract

Although carbon nanotube (CNT) transistors have been promoted for years as a replacement for silicon technology, there is limited theoretical work and no experimental reports on how nanotubes will perform at sub-10 nm channel lengths. In this manuscript, we demonstrate the first sub-10 nm CNT transistor, which is shown to outperform the best competing silicon devices with more than four times the diameter-normalized current density (2.41 mA/μm) at a low operating voltage of 0.5 V. The nanotube transistor exhibits an impressively small inverse subthreshold slope of 94 mV/decade—nearly half of the value expected from a previous theoretical study. Numerical simulations show the critical role of the metal–CNT contacts in determining the performance of sub-10 nm channel length transistors, signifying the need for more accurate theoretical modeling of transport between the metal and nanotube. The superior low-voltage performance of the sub-10 nm CNT transistor proves the viability of nanotubes for consideration in future aggressively scaled transistor technologies.