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Electrical Control of Uniformity in Quantum Dot Devices
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  • Marcel Meyer
    Marcel Meyer
    QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
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    Orcidhttps://orcid.org/0000-0002-7832-5927
  • Corentin Déprez
    Corentin Déprez
    QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
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  • Timo R. van Abswoude
    Timo R. van Abswoude
    QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
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  • Ilja N. Meijer
    Ilja N. Meijer
    QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
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    Orcidhttps://orcid.org/0000-0003-0516-8446
  • Dingshan Liu
    Dingshan Liu
    QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
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    Orcidhttps://orcid.org/0000-0003-3410-9111
  • Chien-An Wang
    Chien-An Wang
    QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
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  • Saurabh Karwal
    Saurabh Karwal
    QuTech and Netherlands Organisation for Applied Scientific Research (TNO), PO Box 155, 2600 AD Delft, The Netherlands
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  • Stefan Oosterhout
    Stefan Oosterhout
    QuTech and Netherlands Organisation for Applied Scientific Research (TNO), PO Box 155, 2600 AD Delft, The Netherlands
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  • Francesco Borsoi
    Francesco Borsoi
    QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
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    Orcidhttps://orcid.org/0000-0001-9398-7614
  • Amir Sammak
    Amir Sammak
    QuTech and Netherlands Organisation for Applied Scientific Research (TNO), PO Box 155, 2600 AD Delft, The Netherlands
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  • Nico W. Hendrickx
    Nico W. Hendrickx
    QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
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  • Giordano Scappucci
    Giordano Scappucci
    QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
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    Orcidhttps://orcid.org/0000-0003-2512-0079
  • Menno Veldhorst*
    Menno Veldhorst
    QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
    *Email for M.V.: [email protected]
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Nano Letters

Cite this: Nano Lett. 2023, 23, 7, 2522–2529
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https://doi.org/10.1021/acs.nanolett.2c04446
Published March 28, 2023

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Abstract

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Highly uniform quantum systems are essential for the practical implementation of scalable quantum processors. While quantum dot spin qubits based on semiconductor technology are a promising platform for large-scale quantum computing, their small size makes them particularly sensitive to their local environment. Here, we present a method to electrically obtain a high degree of uniformity in the intrinsic potential landscape using hysteretic shifts of the gate voltage characteristics. We demonstrate the tuning of pinch-off voltages in quantum dot devices over hundreds of millivolts that then remain stable at least for hours. Applying our method, we homogenize the pinch-off voltages of the plunger gates in a linear array for four quantum dots, reducing the spread in pinch-off voltages by one order of magnitude. This work provides a new tool for the tuning of quantum dot devices and offers new perspectives for the implementation of scalable spin qubit arrays.

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Spin qubits in semiconductor quantum dots are a promising platform for quantum information processing. (1−4) Group IV semiconductors such as silicon and germanium can be isotopically purified, (5) enabling long quantum coherence (6,7) high-fidelity single-qubit (8−10) and two-qubit gates (11−13) as well as multi-qubit operation. (14,15) Spin qubits can be operated at comparatively high temperatures, (16−18) and their compatibility with semiconductor technologies spurred the realization of qubits made in industrial foundries. (19,20) However, implementing more than a few qubits on a single chip remains extremely challenging.

Variations, in particular at the nanoscale, may lead to significant alterations of the relevant device metrics, (1,2,21) such as the voltage needed to load a single electron to be used as a spin qubit. These variations can complicate the tuning of initialization, control, or readout and potentially form a roadblock for larger systems. Additionally, qubit-to-qubit variability may require the use of individual control electronics for each qubit, as is common practice in current experimental implementations, thus challenging the scalability. While several proposals have been put forward to scale quantum dot qubits, (2,22−24) in all cases a high level of device uniformity is critical in their realization.

For semiconductor quantum dot qubits, the uniformity of the potential landscape is the key parameter that dictates the number of control voltages required per qubit. Ideally, a few voltages would suffice to induce a highly regular potential landscape as, drawn in Figure 1b. Yet, potential fluctuations are naturally present, as illustrated in Figure 1c. They can be caused by defects, charge traps and mechanical stress induced by the deposition of metallic gates, (25,26) as well as variations in material growth or in the exact shape of the gates. The development of devices based on quantum wells buried in heterostructures, similar to that sketched in Figure 1a, already has led to a drastic improvement of the uniformity compared to metal oxide semiconductor systems. (27) This has enabled the control of up to 16 quantum dots in a 4 × 4 array with shared gate control. (28) However, significant variations in the quantum dot potential landscape are still commonly observed. (28−30) This raises the question whether material (4) and fabrication development (20,28,31,32) will suffice to reach the required uniformity to operate large qubit arrays.

Figure 1

Figure 1. Fluctuations in the potential landscape in semiconductor quantum dot devices. (a) Schematic of typical semiconductor heterostructures with buried quantum wells studied. The metallic gate electrodes colored in yellow and blue represent the barrier (B) and plunger gates (P) of a quantum dot array, respectively. (b) Potential landscape in an ideal device with shared gate control. The application of the same voltage VP/B on all plunger/barrier gates leads to a regular potential landscape with negligible fluctuations compared to those of the other relevant energy scales (α denotes the gate lever arm). The quantum dots all have the same charge configuration. (c) Potential landscape in state-of-the-art devices with shared gate control. The application of the same voltage VP/B on all plunger/barrier gates leads to an irregular potential landscape due to local fluctuations, which are often comparable to or larger than the charging energy EC. Consequently, the quantum dots have different charge configurations. (d) Typical variations in the pinch-off characteristic of the plunger gates in a state-of-the-art linear quantum dot array (device A), nominally identical with that displayed in in Figure 4a, just after a cooldown. The pinch-off voltage Vthres is defined as the gate voltage for which the current reaches Ithres = 50 pA at a bias of |Vsd| = 100 μV. Here, the pinch-off voltages spread over a voltage range ΔVthres = 226 mV.

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Here, we present an alternative method and demonstrate electrical control of uniformity in quantum dot devices. Our approach takes advantage of the gate voltage hysteresis, a ubiquitous effect observed in semiconductor heterostructures, that is mostly considered as a limitation in the tune-up of quantum dots. It manifests in shifts of the gate voltage characteristics and is commonly explained by a buildup of charges at the interface between the semiconductor barrier and the dielectrics, which then alter the electric field in the buried quantum well. (33−39) We unveil the hysteresis and its effects on the potential landscape beneath the gates by studying how pinch-off characteristics evolve with the application of tailored stress voltage sequences. This method allows us to tune those pinch-off voltages over hundreds of millivolts, after which they remain stable at least on the time scale of hours. We then apply our findings to homogeneize the plunger gate pinch-off characteristics in a linear quantum dot array, reducing potential fluctuations in the quantum well underneath the corresponding gates.

The gate voltage required to confine a single electron or hole typically varies between quantum dots in an array, as it is dependent on the local electrostatic environment. These fluctuations also affect the pinch-off curve as exemplarily depicted for sweeping the four plunger gates of a linear quantum dot device (similar to that shown in Figure 4a) in Figure 1d. The curves reveal the local depletion of a conducting path through the quantum well and experimentally can be obtained in a very short time compared to the time required for the formation of a well-defined quantum dot. Therefore, we will employ pinch-off characteristics in the following to efficiently estimate variations in the potential landscape on the length scale of single quantum dots. In particular, we focus on the pinch-off voltages Vthres defined as the gate voltages at which a current of Ithres = 50 pA is reached for an applied source drain bias of |Vsd| = 100 μV.

We study devices in 28Si/SiGe heterostructures (40) and investigate how the pinch-off voltage of a single gate evolves depending on the previously applied gate voltages. To that end, we conduct systematic transport measurements at 4.2 K similar to sequences in refs (41−44) following the procedure depicted in Figure 2a. First a stress voltage Vstress is applied to the gate under study for a time tstress = 1 min. Then the gate voltage is swept back until the pinch-off condition I = Ithres is met. This sequence is repeated several times with evolving stress voltages to measure the evolution of Vthres as a function of Vstress. First, the applied stress voltage Vstress is decreased stepwise to be increased gradually again after reaching a reversal point Vstress = Vstressrev.

Figure 2

Figure 2. Hysteresis of the pinch-off characteristics. (a) Schematics of the measurement sequence used to probe the hysteretic behavior of the pinch-off voltage Vthres of a single gate. Vthres, i.e. the voltage when the current reaches Ithres = 50 pA at a bias voltage |Vsd| = 100 μV, is measured after application of successive stress voltages Vstress for tstress = 1 min. The measurements start with decreasing Vstress. Upon reaching Vstress = Vstressrev, the direction is reversed and a sequence of increasing Vstress is applied. (b) Evolution of the pinch-off voltage Vthres of the sensor plunger gate S1 as a function of the stress voltage Vstress for two different cooldowns of device B. The measurement cycle is sketched in the top illustration. The square and the circle mark the starting point and the ending point of the cycles, respectively. The star indicates the point Vstressrev where the stress voltage sequence is reversed. Vstress is first decreased before being increased again after Vstressrev = −3.7 V. Both sets of points draw hysteresis cycles which overlap. The remaining gates that are needed to form a conductive channel are set to V0 = 1.2 V. (c) (Vstress, Vthres) hysteresis cycles measured successively for plunger gate P1 in device A. The points where the stress voltage sequences are reversed (stars) and ended (circles) are changed between each cycle. Note that for the fifth iteration, the stress voltage sequence with increasing Vstress was stopped purposely when Vthres ≃ 1 V. All other gates were set to V0 = 1.704 V.

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Figure 2b shows the resulting pinch-off voltage evolution for a plunger gate Pi that is part of a linear quantum dot array for two different cooldowns (blue and pink curve, respectively). In these cases, Vstress is first lowered stepwise from Vstress = 1.05 V to Vstressrev = −3.7 V. We observe that up to Vstress > −2.0 V the pinch-off voltages Vthres stay within ±15 mV of the first pinch-off voltage Vthres0 = 1.06 V, forming a plateau. Then, they drop down rapidly to Vthres = 0.83 V. At Vstressrev = −3.7 V, the sweep direction is reversed and we start to increase Vstress progressively. However, we do not observe a reversed behavior. Instead, from Vstress = −2.7 V to Vstress = 0.9 V, the pinch-off voltages increase by less than 25 mV, forming a second plateau. Only when Vstress = 1.0 (1.1) V for the first (second) cooldown does Vthres start to increase steeply again. The ensembles of (Vstress, Vthres) values draw typical hysteresis cycles with plateaus marking the ranges of applicable gate voltages over which the pinch-off voltage is not significantly changing. Furthermore, Figure 2b highlights the effect of thermal cycling on these measurements and reveals a remarkable overlap of the hysteresis cycles measured during two different cooldowns. A high degree of similarity is also observed when comparing successive measurements performed using the same stress voltage sequence as shown in Figure S2 in the Supporting Information for gate S of device D. This suggests that the underlying process has a deterministic nature.

Similar experiments performed on another sample with varying reversal points Vstressrev result in the cycles plotted in Figure 2c. The shapes of the curves are nearly identical for each iteration. Again, we observe plateaus where the pinch-off voltage deviates by less than 50 mV from its first value. Yet, the position of the plateaus varies with the chosen Vstressrev. The pinch-off voltage plateaus can be shifted by up to |ΔVthres| = 290 mV for the lower plateau and by up to |ΔVthres| = 400 mV for the upper plateau. Overall, Figure 2b,c suggests that by applying a dedicated voltage sequence the pinch-off voltage can be adjusted on demand to chosen targets and thus that the intrinsic potential landscape underneath the gates can be tuned.

We also note that similar hysteretic behaviors, with sample-dependent variations of the exact shape of the (Vstress, Vthres) curves, are consistently found in several Si/SiGe devices (e.g., device D gate S shown in Figure S2 in the Supporting Information) as well as in samples made from Ge/SiGe heterostructures (see Figure S3 in the Supporting Information), suggesting a common underlying mechanism. The observed reproducibility and the large control window of the pinch-off voltage are the foundations of our approach to homogenize the potential landscape below an ensemble of gates.

However, the electrical tuning of the intrinsic potential uniformity is of practical interest only if the resulting potential landscape remains stable afterward. Therefore, we study how the pinch-off voltage evolves in time after stopping the hysteresis measurement cycle at varying points. The procedure followed is depicted in Figure 3a. The gate voltage is swept back and forth continuously to determine the voltage range [Vthres−(t),Vthres+(t)] over which the current stays in a small range [Ithres – ΔI, Ithres + ΔI] around the current threshold Ithres as a function of time t. For each sweep [Vthres−(t),Vthres+(t)] a linear regression I = m × V + b with fitting parameters m and b is applied from which the pinch-off voltage Vthres(t) = (Ithres – b)/m is extracted. Figure 3a shows the time evolution directly after the application of decreasing (violet and blue) and increasing (light pink) stress voltages. For comparison, we also plot how the pinch-off voltage evolves right after a cooldown without prior application of a stress voltage sequence (dark pink). For decreasing Vstress sequences, the pinch-off voltages converge into steady states after initial decays and the time evolution exhibits random abrupt jumps. For the situation where no stress voltage or increasing stress voltages Vstress are applied, no significant variations of Vthres are observed. The relative evolution depicted in Figure 3b reveals that, for t > 2 h, the voltage fluctuations are similar for all three situations. This is confirmed by extracting the standard deviations of Vthres for experiments with and without application of stress voltage sequences, which are σstress = 0.4 mV (increasing Vstress), σstress = 1.0 and 0.6 mV (decreasing Vstress), and σno stress = 0.8 mV (no stress), respectively. These experiments suggest that after a potential initial transient regime there is no change in the stability of the device due to the electrical tuning. This stability is observed for at least 1 h and up to 3 h depending on the voltage sequence applied.

Figure 3

Figure 3. Stability of the pinch-off voltage after tuning. (a) Schematic representation of the procedure used to probe the time stability of the pinch-off voltage of a single gate. The gate voltage is continuously swept back and forth to detect the voltage range [Vthres−(t),Vthres+(t)] over which the current stays between Ithres – ΔI and Ithres + ΔI with ΔI ∈ {10 pA, 25 pA}. From each sweep Vthres(t) is extracted by linear regression. (b) Time evolution of Vthres prior to any application of stress voltages (dark pink) and after tuning via application of increasing Vstress with Vstressrev > 0 V (light pink) or decreasing Vstress with Vstressrev < 0 V (violet and blue). The curves are obtained for sensor plunger gate S in device C, except for the pink curve which is obtained for sensor plunger gate S in device D. Ithres = 50 pA, except for the blue curve of decreasing stress, where it was defined as Ithres = 30 pA, which provided a more robust analysis. (c) Relative variations ΔVthres(t) = Vthres(t) – Vthres(t = 3 h) of the data shown in (b).

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Next we apply our findings and probe the capability to homogenize the pinch-off voltages Vthresi of a group of plunger gates Pi with i in [1,4] in a quantum dot array. Figure 4a displays the device studied, which has a geometry similar to linear quantum dot arrays in refs (12,15,29,and45). The pinch-off characteristics recorded prior to the tuning sequence are depicted in the left panel of Figure 4c and show a spread ΔVthres = max(Vthres) – min(Vthres) of 153 mV. Employing increasing gate voltage stress, we tune the individual plunger pinch-off voltages to the target value Vtarget = 1.05 V chosen before starting the tuning. Figure 4b illustrates the procedure followed for the specific case of two gates. A schematic representation including all four gates is displayed in Figure S4 in the Supporting Information. Vstress is gradually increased in n steps. For each Vstressn, the plunger gates are sequentially stressed, measured, and parked ΔVpark = 50 mV above their latest pinch-off voltage, where they remain until the next stress voltage Vstressn+1 = Vstressn + ΔVstress is selected. When a pinch-off voltage Vthresi crosses the target voltage Vtarget, the corresponding plunger gate Pi is henceforth no longer stressed. A full automated round of this sequence finishes after all pinch-off voltages are larger than the target voltage. The complete procedure is repeated two times with a stress voltage resolution of ΔVstress = 25 mV taking approximately 9 h in total. All applied stress voltages and measured pinch-off voltages are visualized in the panels of Figure 4d. After each repetition a pinch-off characterization is performed with the resulting curves depicted in Figure 4c. During the first round the pinch-off voltages shift toward the target voltage Vtarget (indicated by the red dashed line), finally spreading in a range of ΔVthres = 86 mV around it. This spread is further reduced by the following iteration, reaching a final value of ΔVthres = 20 mV. Afterward the plunger pinch-off characteristics are observed to remain stable at least for 20 min (see Figure S5 in the Supporting Information).

Figure 4

Figure 4. Homogenization of the potential landscape below the plunger gates of a linear quantum dot array. (a) Scanning electron micrograph of a linear quantum dot array. The plunger, barrier, accumulation, and screening gates are colored in blue, yellow, orange, and violet, respectively. The current flow is depicted by the dashed line. We aim at equalizing the pinch-off voltages of the plunger gates Pi. (b) Schematics of the strategy followed illustrated with only two gates for clarity. Note that here, in contrast to the illustration in Figure 2a, the pinch-off voltage Vthres is detected through lowering the gate voltage until I = Ithres. (c) Evolution of the pinch-off characteristics in device A after two iterations of the tuning procedure. The target voltage Vtarget = 1.05 V is marked by a red dashed line. After two iterations the spread of the pinch-off voltage ΔVthres is reduced from 153 mV to 20 mV. (d) Evolution of Vthres for each gate while Vstress is increased during the tuning procedure. The red dashed line indicates the target pinch-off voltage Vtarget = 1.05 V. The stressing on each gate is stopped when its pinch-off voltage becomes larger than Vtarget. The coloring of the data points encodes the time evolution of the stress and pinch-off voltages of the gates during each iteration.

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To discuss our results and their implications for the tuning of quantum dot arrays, we assume that pinch-off voltages constitute a witness of the intrinsic potential landscape in the quantum well. Thus, we state that the observed tunability of pinch-off voltages also directly translates into a similar tunability of quantum dot chemical potentials. This statement is supported by a study of the effect of stress voltages on charge transitions of a quantum dot discussed in section VII in the Supporting Information. We find that the quantum dot potential can be tuned analogously to the threshold voltage Vthres by applying stress voltage sequences on the quantum dot plunger gate.

This motivates us to compare the final spread of the pinch-off voltages to the degree of uniformity needed to load an array of quantum dots with a single electron at each site using a single common gate voltage. Reaching such uniformity would require the potential fluctuations below the gates to be smaller than the average charging voltage VC = EC/α that is needed to alter the charge occupation, with EC being the charging energy and α the gate lever arm. Charging voltages typically range from 10 to 60 mV in devices similar to that under study. (27,29,45,46) Consequently, the final spread ΔVthres = 20 mV reached after electrical tuning promises a path toward the homogenization of quantum dot potentials inside an array. Even smaller spreads might be achievable by decreasing the stress voltage resolution ΔVstress. We envision that a similar method could be used to tune the potential underneath all plunger and all barrier gates simultaneously. It could also allow equalizing the interdot tunnel couplings and reaching an energy landscape similar to that in Figure 1b.

At the same time, optimization of the automated procedure could lead to a significant increase of the tuning efficiency. Such an optimized procedure may be obtained by dividing the tuning into coarse and fine steps and exploring different stressing times and thereby could drastically reduce the tuning time. Additionally, utilizing a model to predict the effect of the next stress voltage could further minimize the number of steps required to reach the target potentials, and simultaneous tuning of multiple gates may be envisioned in larger quantum dot arrays.

Adapted tuning procedures may also be designed for scalable device architectures. In a crossbar gate architecture, (24,28) one could envision applying different stressing voltages on different sets of gates such that only close to the crossing points of these gates the combined electric field would be strong enough to shift the intrinsic potential. This would allow parallel but individual stressing of selected sites in a row-by-row manner. Another degree of selectivity might be provided through biasing of purposely isolated parts of the quantum well. Effectively, this would locally change the gates’ reference potential and thereby locally alter the effect of the stressing voltages applied to them. Further work is needed to confirm the viability of these approaches.

Also, a better understanding of the underlying mechanism of the hysteresis would be valuable to exploit it most efficiently. A possible origin might be the trapping and detrapping of charge in or close to the dielectric capping layer caused by the application of stress voltages. (33−38) For example, a positive stress voltage might enable the tunneling of electrons from the quantum well or traps underneath nonstressed gates to traps underneath the stressed gate. These traps could be bound states in the nonoxidized part of the silicon capping layer or at its SiGe interface. They can be induced by charge defects in the gate oxide (47) or emerge due to mechanical stress originating from the deposition of metallic gates. (25,26) Also, charge trapping into and out of unpassivated silicon and germanium dangling bonds, (48−50) charge trapping in the oxide itself mediated by leakage currents, (44,51−53) or movement of mobile ions (54) might be underlying the hysteresis. In all cases, when the gate voltage stress is removed, the charges would be expected to be immobile at the device operation temperature and would cause local shifts in the intrinsic potential landscape observable as alterations in the pinch-off characteristics. This tunneling and trapping of charge also would be highly similar to the principle used to operate modern flash memories (based on electrically erasable programmable read-only memories), which encode their stored information in pinch-off voltages and rely on gate stacks specifically engineered for that purpose. (53,55) They could inspire new heterostructures and gate stacks with dedicated trapping layers, further refining the tunability of the potential landscape using the gate voltage hysteresis.

In conclusion, we have presented a new method to increase the electrostatic potential uniformity in quantum dot devices electrically. We demonstrate that we can take advantage of hysteretic shifts in gate voltage characteristics to deliberately tune pinch-off voltages across a wide range of more than 500 mV by applying stress voltage sequences. The resulting states remain stable on the time scale of hours. We also show that the chemical potential of single quantum dots can be tuned using similar procedures. Utilizing our method, we have shifted and equalized the pinch-off voltages of four plunger gates in a linear quantum dot array to a predetermined target voltage. Although most of our results were obtained in Si/SiGe heterostructures, other measurements indicate that the effect and method also can be used in other heterostructure materials like Ge/SiGe. Our work opens up a new path to increase uniformity in quantum dot based spin qubits. It may enable reducing overheads in tuning and control, making the implementation of scalable architectures more feasible in practice.

Data Availability

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The data and analysis supporting this work are openly available in a public Zenodo repository at 10.5281/zenodo.7746206. (56)

Supporting Information

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The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acs.nanolett.2c04446.

  • Materials and device fabrication details, description of the experimental setup, details on the experimental procedures, SEM images of devices nominally identical with those used in this work, presentation of ten consecutive hysteresis cycles, hysteresis cycles obtained in Ge/SiGe single hole transistor structures, full schematics of the stress voltage sequence employed for tuning the plunger gate pinch-off voltages in a linear array, stability of the four plunger pinch-off characteristics after the tuning procedure presented, analysis of the effect of stress voltages on coulomb-blockade oscillations, table of samples investigated and corresponding reversal points (PDF)

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Author Information

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  • Corresponding Author
    • Menno Veldhorst - QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands;  Email: [email protected]
  • Authors
    • Marcel Meyer - QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands;  Orcidhttps://orcid.org/0000-0002-7832-5927
    • Corentin Déprez - QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
    • Timo R. van Abswoude - QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
    • Ilja N. Meijer - QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands;  Orcidhttps://orcid.org/0000-0003-0516-8446
    • Dingshan Liu - QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands;  Orcidhttps://orcid.org/0000-0003-3410-9111
    • Chien-An Wang - QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
    • Saurabh Karwal - QuTech and Netherlands Organisation for Applied Scientific Research (TNO), PO Box 155, 2600 AD Delft, The Netherlands
    • Stefan Oosterhout - QuTech and Netherlands Organisation for Applied Scientific Research (TNO), PO Box 155, 2600 AD Delft, The Netherlands
    • Francesco Borsoi - QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands;  Orcidhttps://orcid.org/0000-0001-9398-7614
    • Amir Sammak - QuTech and Netherlands Organisation for Applied Scientific Research (TNO), PO Box 155, 2600 AD Delft, The Netherlands
    • Nico W. Hendrickx - QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands
    • Giordano Scappucci - QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands;  Orcidhttps://orcid.org/0000-0003-2512-0079
  • Notes
    The authors declare the following competing financial interest(s): M.V. and N.W.H. are inventors on a patent application related to this work (PCT/N L2022/050377), filing date 30 June 2022. The other authors declare no competing financial interest.

Acknowledgments

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We gratefully acknowledge D. Michalak, D. Degli-Esposti, and M. Mehmandoost for sharing their expertise, their insights on the underlying physics, and their valuable advice. We also acknowledge S. Philips and F. K. Unseld for their help on the Si/SiGe device design. We thank L. M. K. Vandersypen for his feedback as well as all the members of the Veldhorst and Vandersypen group for stimulating discussions. We thank J. D. Mensingh and N. P. Alberts for their technical support with the experimental setups and S. L. de Snoo for software support. We acknowledge support through an ERC Starting Grant and through an NWO projectruimte. This research was supported by the European Union’s Horizon 2020 research and innovation programme under the Grant Agreement No. 951852 (QLSI project). Research was sponsored by the Army Research Office (ARO) and was accomplished under Grant No. W911NF-17-1-0274. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the Army Research Office (ARO) or the U.S. Government. The U.S. Government is authorized to reproduce and distribute reprints for government purposes notwithstanding any copyright notation herein.

References

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This article references 56 other publications.

  1. 1
    Zwanenburg, F. A.; Dzurak, A. S.; Morello, A.; Simmons, M. Y.; Hollenberg, L. C. L.; Klimeck, G.; Rogge, S.; Coppersmith, S. N.; Eriksson, M. A. Silicon quantum electronics. Rev. Mod. Phys. 2013, 85, 961,  DOI: 10.1103/RevModPhys.85.961
    Google Scholar
    1
    Silicon quantum electronics
    Zwanenburg, Floris A.; Dzurak, Andrew S.; Morello, Andrea; Simmons, Michelle Y.; Hollenberg, Lloyd C. L.; Klimeck, Gerhard; Rogge, Sven; Coppersmith, Susan N.; Eriksson, Mark A.
    Reviews of Modern Physics (2013), 85 (3), 961-1019CODEN: RMPHAT; ISSN:0034-6861. (American Physical Society)
    This review describes recent groundbreaking results in Si, Si/SiGe, and dopant-based quantum dots, and it highlights the remarkable advances in Si-based quantum physics that have occurred in the past few years. This progress has been possible thanks to materials development of Si quantum devices, and the phys. understanding of quantum effects in silicon. Recent crit. steps include the isolation of single electrons, the observation of spin blockade, and single-shot readout of individual electron spins in both dopants and gated quantum dots in Si. Each of these results has come with physics that was not anticipated from previous work in other material systems. These advances underline the significant progress toward the realization of spin quantum bits in a material with a long spin coherence time, crucial for quantum computation and spintronics.
  2. 2
    Vandersypen, L. M. K.; Bluhm, H.; Clarke, J. S.; Dzurak, A. S.; Ishihara, R.; Morello, A.; Reilly, D. J.; Schreiber, L. R.; Veldhorst, M. Interfacing spin qubits in quantum dots and donors - hot, dense, and coherent. npj Quantum Inf 2017, 3, 34,  DOI: 10.1038/s41534-017-0038-y
    Google Scholar
    There is no corresponding record for this reference.
  3. 3
    Scappucci, G.; Kloeffel, C.; Zwanenburg, F. A.; Loss, D.; Myronov, M.; Zhang, J.-J.; De Franceschi, S.; Katsaros, G.; Veldhorst, M. The germanium quantum information route. Nature Reviews Materials 2021, 6, 926,  DOI: 10.1038/s41578-020-00262-z
    Google Scholar
    3
    The germanium quantum information route
    Scappucci, Giordano; Kloeffel, Christoph; Zwanenburg, Floris A.; Loss, Daniel; Myronov, Maksym; Zhang, Jian-Jun; De Franceschi, Silvano; Katsaros, Georgios; Veldhorst, Menno
    Nature Reviews Materials (2021), 6 (10), 926-943CODEN: NRMADL; ISSN:2058-8437. (Nature Portfolio)
    A review. In the effort to develop disruptive quantum technologies, germanium is emerging as a versatile material to realize devices capable of encoding, processing and transmitting quantum information. These devices leverage the special properties of holes in germanium, such as their inherently strong spin-orbit coupling and their ability to host superconducting pairing correlations. In this Review, we start by introducing the physics of holes in low-dimensional germanium structures, providing key insights from a theor. perspective. We then examine the materials-science progress underpinning germanium-based planar heterostructures and nanowires. We go on to review the most significant exptl. results demonstrating key building blocks for quantum technol., such as an elec. driven universal quantum gate set with spin qubits in quantum dots and superconductor-semiconductor devices for hybrid quantum systems. We conclude by identifying the most promising avenues towards scalable quantum information processing in germanium-based systems.
  4. 4
    Scappucci, G.; Taylor, P. J.; Williams, J. R.; Ginley, T.; Law, S. Crystalline materials for quantum computing: Semiconductor heterostructures and topological insulators exemplars. MRS Bull. 2021, 46, 596,  DOI: 10.1557/s43577-021-00147-8
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    4
    Crystalline materials for quantum computing and Semiconductor heterostructures and topological insulators exemplars
    Scappucci, G.; Taylor, P. J.; Williams, J. R.; Ginley, T.; Law, S.
    MRS Bulletin (2021), 46 (7), 596-606CODEN: MRSBEA; ISSN:1938-1425. (Springer International Publishing AG)
    Abstr.: High-purity cryst. solid-state materials play an essential role in various technologies for quantum information processing, from qubits based on spins to topol. states. New and improved cryst. materials emerge each year and continue to drive new results in exptl. quantum science. This article summarizes the opportunities for a selected class of cryst. materials for qubit technologies based on spins and topol. states and the challenges assocd. with their fabrication. We start by describing semiconductor heterostructures for spin qubits in gate-defined quantum dots and benchmark GaAs, Si, and Ge, the three platforms that demonstrated two-qubit logic. We then examine novel topol. nontrivial materials and structures that might be incorporated into superconducting devices to create topol. qubits. We review topol. insulator thin films and move onto topol. cryst. materials, such as PbSnTe, and its integration with Josephson junctions. We discuss advances in novel and specialized fabrication and characterization techniques to enable these. We conclude by identifying the most promising directions where advances in these material systems will enable progress in qubit technol.
  5. 5
    Itoh, K. M.; Watanabe, H. Isotope engineering of silicon and diamond for quantum computing and sensing applications. MRS Commun. 2014, 4, 143– 157,  DOI: 10.1557/mrc.2014.32
    Google Scholar
    5
    Isotope engineering of silicon and diamond for quantum computing and sensing applications
    Itoh, Kohei M.; Watanabe, Hideyuki
    MRS Communications (2014), 4 (4), 143-157CODEN: MCROF8; ISSN:2159-6867. (Cambridge University Press)
    Some of the stable isotopes of silicon and carbon have zero nuclear spin, whereas many of the other elements that constitute semiconductors consist entirely of stable isotopes that have nuclear spins. Silicon and diamond crystals composed of nuclear-spin-free stable isotopes (28Si, 30Si, or 12C) are considered to be ideal host matrixes to place spin quantum bits (qubits) for quantum-computing and -sensing applications, because their coherent properties are not disrupted thanks to the absence of host nuclear spins. The present paper describes the state-of-the-art and future perspective of silicon and diamond isotope engineering for development of quantum information-processing devices.
  6. 6
    Veldhorst, M.; Hwang, J. C. C.; Yang, C. H.; Leenstra, A. W.; de Ronde, B.; Dehollain, J. P.; Muhonen, J. T.; Hudson, F. E.; Itoh, K. M.; Morello, A.; Dzurak, A. S. An addressable quantum dot qubit with fault-tolerant control-fidelity. Nat. Nanotechnol. 2014, 9, 981,  DOI: 10.1038/nnano.2014.216
    Google Scholar
    6
    An addressable quantum dot qubit with fault-tolerant control-fidelity
    Veldhorst, M.; Hwang, J. C. C.; Yang, C. H.; Leenstra, A. W.; de Ronde, B.; Dehollain, J. P.; Muhonen, J. T.; Hudson, F. E.; Itoh, K. M.; Morello, A.; Dzurak, A. S.
    Nature Nanotechnology (2014), 9 (12), 981-985CODEN: NNAABX; ISSN:1748-3387. (Nature Publishing Group)
    Exciting progress towards spin-based quantum computing has recently been made with qubits realized using N-vacancy centers in diamond and P atoms in Si. For example, long coherence times were made possible by the presence of spin-free isotopes of C and Si. However, despite promising single-atom nanotechnologies, there remain substantial challenges in coupling such qubits and addressing them individually. Conversely, lithog. defined quantum dots have an exchange coupling that can be precisely engineered, but strong coupling to noise has severely limited their dephasing times and control fidelities. Here, we combine the best aspects of both spin qubit schemes and demonstrate a gate-addressable quantum dot qubit in isotopically engineered Si with a control fidelity of 99.6%, obtained via Clifford-based randomized benchmarking and consistent with that required for fault-tolerant quantum computing. This qubit has dephasing time T2* = 120 μs and coherence time T2 = 28 ms, both orders of magnitude larger than in other types of semiconductor qubit. By gate-voltage-tuning the electron g*-factor we can Stark shift the ESR frequency by more than 3,000 times the 2.4 kHz ESR linewidth, providing a direct route to large-scale arrays of addressable high-fidelity qubits that are compatible with existing manufg. technologies.
  7. 7
    Stano, P.; Loss, D. Review of performance metrics of spin qubits in gated semiconducting nanostructures. Nature Review Physics 2022, 4, 672,  DOI: 10.1038/s42254-022-00484-w
    Google Scholar
    There is no corresponding record for this reference.
  8. 8
    Dehollain, J. P.; Muhonen, J. T.; Blume-Kohout, R.; Rudinger, K. M.; King Gamble, J.; Nielsen, E.; Laucht, A.; Simmons, S.; Kalra, R.; Dzurak, A. S.; Morello, A. Optimization of a solid-state electron spin qubit using gate set tomography. New J. Phys. 2016, 18, 103018,  DOI: 10.1088/1367-2630/18/10/103018
    Google Scholar
    8
    Optimization of a solid-state electron spin qubit using gate set tomography
    Dehollain, Juan P.; Muhonen, Juha T.; Blume-Kohout, Robin; Rudinger, Kenneth M.; Gamble, John King; Nielsen, Erik; Laucht, Arne; Simmons, Stephanie; Kalra, Rachpon; Dzurak, Andrew S.; Morello, Andrea
    New Journal of Physics (2016), 18 (Oct.), 103018/1-103018/9CODEN: NJOPFM; ISSN:1367-2630. (IOP Publishing Ltd.)
    State of the art qubit systems are reaching the gate fidelities required for scalable quantum computation architectures. Further improvements in the fidelity of quantum gates demands characterization and benchmarking protocols that are efficient, reliable and extremely accurate. Ideally, a benchmarking protocol should also provide information on how to rectify residual errors. Gate set tomog. (GST) is one such protocol designed to give detailed characterization of as-built qubits. We implemented GST on a high-fidelity electron-spin qubit confined by a single 31P atom in 28Si. The results reveal systematic errors that a randomized benchmarking anal. could measure but not identify, whereas GST indicated the need for improved calibration of the length of the control pulses. After introducing this modification, we measured a new benchmark av. gate fidelity of 99.942(8)%, an improvement on the previous value of 99.90(2)%. Furthermore, GST revealed high levels of non-Markovian noise in the system, which will need to be understood and addressed when the qubit is used within a fault-tolerant quantum computation scheme.
  9. 9
    Yoneda, J.; Takeda, K.; Otsuka, T.; Nakajima, T.; Delbecq, M. R.; Allison, G.; Honda, T.; Kodera, T.; Oda, S.; Hoshi, Y.; Noritaka, U.; Itoh, K. M.; Tarucha, S. A quantum-dot spin qubit with coherence limited by charge noise and fidelity higher than 99.9%. Nat. Nanotechnol. 2018, 13, 102,  DOI: 10.1038/s41565-017-0014-x
    Google Scholar
    9
    A quantum-dot spin qubit with coherence limited by charge noise and fidelity higher than 99.9%
    Yoneda, Jun; Takeda, Kenta; Otsuka, Tomohiro; Nakajima, Takashi; Delbecq, Matthieu R.; Allison, Giles; Honda, Takumu; Kodera, Tetsuo; Oda, Shunri; Hoshi, Yusuke; Usami, Noritaka; Itoh, Kohei M.; Tarucha, Seigo
    Nature Nanotechnology (2018), 13 (2), 102-106CODEN: NNAABX; ISSN:1748-3387. (Nature Research)
    The isolation of qubits from noise sources, such as surrounding nuclear spins and spin-elec. susceptibility, has enabled extensions of quantum coherence times in recent pivotal advances towards the concrete implementation of spin-based quantum computation. In fact, the possibility of achieving enhanced quantum coherence has been substantially doubted for nanostructures due to the characteristic high degree of background charge fluctuations. Still, a sizeable spin-elec. coupling will be needed in realistic multiple-qubit systems to address single-spin and spin-spin manipulations. Here, we realize a single-electron spin qubit with an isotopically enriched phase coherence time (20 μs) and fast elec. control speed (up to 30 MHz) mediated by extrinsic spin-elec. coupling. Using rapid spin rotations, we reveal that the free-evolution dephasing is caused by charge noise - rather than conventional magnetic noise - as highlighted by a 1/f spectrum extended over seven decades of frequency. The qubit exhibits superior performance with single-qubit gate fidelities exceeding 99.9% on av., offering a promising route to large-scale spin-qubit systems with fault-tolerant controllability. Quantum control on an isotopically enriched Si spin qubit is demonstrated with ultrahigh gate fidelities and long coherence times - even in the presence of sizeable charge noise.
  10. 10
    Lawrie, W. I. L.; Russ, M.; van Riggelen, F.; Hendrickx, N. W.; de Snoo, S. L.; Sammak, A.; Vandersypen, L. M. K.; Scappucci, G.; Veldhorst, M. Simultaneous driving of semiconductor spin qubits at the fault-tolerant threshold. arXiv, 2109.07837 (2021).
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    There is no corresponding record for this reference.
  11. 11
    Mądzik, M.; Asaad, S.; Youssry, A.; Joecker, B.; Rudinger, K. M.; Nielsen, E.; Young, K. C.; Proctor, T. J.; Baczewski, A. D.; Laucht, A.; Schmitt, V.; Hudson, F. E.; Itoh, K. M.; Jakob, A. M.; Johnson, B. C.; Jamieson, D. N.; Dzurak, A. S.; Ferrie, C.; Blume-Kohout, R.; Morello, A. Precision tomography of a three-qubit donor quantum processor in silicon. Nature 2022, 601, 348,  DOI: 10.1038/s41586-021-04292-7
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    11
    Precision tomography of a three-qubit donor quantum processor in silicon
    Madzik, Mateusz T.; Asaad, Serwan; Youssry, Akram; Joecker, Benjamin; Rudinger, Kenneth M.; Nielsen, Erik; Young, Kevin C.; Proctor, Timothy J.; Baczewski, Andrew D.; Laucht, Arne; Schmitt, Vivien; Hudson, Fay E.; Itoh, Kohei M.; Jakob, Alexander M.; Johnson, Brett C.; Jamieson, David N.; Dzurak, Andrew S.; Ferrie, Christopher; Blume-Kohout, Robin; Morello, Andrea
    Nature (London, United Kingdom) (2022), 601 (7893), 348-353CODEN: NATUAS; ISSN:1476-4687. (Nature Portfolio)
    Abstr.: Nuclear spins were among the first phys. platforms to be considered for quantum information processing1,2, because of their exceptional quantum coherence3 and at.-scale footprint. However, their full potential for quantum computing has not yet been realized, owing to the lack of methods with which to link nuclear qubits within a scalable device combined with multi-qubit operations with sufficient fidelity to sustain fault-tolerant quantum computation. Here we demonstrate universal quantum logic operations using a pair of ion-implanted 31P donor nuclei in a silicon nanoelectronic device. A nuclear two-qubit controlled-Z gate is obtained by imparting a geometric phase to a shared electron spin4, and used to prep. entangled Bell states with fidelities up to 94.2(2.7)%. The quantum operations are precisely characterized using gate set tomog. (GST)5, yielding one-qubit av. gate fidelities up to 99.95(2)%, two-qubit av. gate fidelity of 99.37(11)% and two-qubit prepn./measurement fidelities of 98.95(4)%. These three metrics indicate that nuclear spins in silicon are approaching the performance demanded in fault-tolerant quantum processors6. We then demonstrate entanglement between the two nuclei and the shared electron by producing a Greenberger-Horne-Zeilinger three-qubit state with 92.5(1.0)% fidelity. Because electron spin qubits in semiconductors can be further coupled to other electrons7-9 or phys. shuttled across different locations10,11, these results establish a viable route for scalable quantum information processing using donor nuclear and electron spins.
  12. 12
    Noiri, A.; Takeda, K.; Nakajima, T.; Kobayashi, T.; Sammak, A.; Scappucci, G.; Tarucha, S. Fast universal quantum gate above the fault-tolerance threshold in silicon. Nature 2022, 601, 338,  DOI: 10.1038/s41586-021-04182-y
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    12
    Fast universal quantum gate above the fault-tolerance threshold in silicon
    Noiri, Akito; Takeda, Kenta; Nakajima, Takashi; Kobayashi, Takashi; Sammak, Amir; Scappucci, Giordano; Tarucha, Seigo
    Nature (London, United Kingdom) (2022), 601 (7893), 338-342CODEN: NATUAS; ISSN:1476-4687. (Nature Portfolio)
    Fault-tolerant quantum computers that can solve hard problems rely on quantum error correction1. One of the most promising error correction codes is the surface code2, which requires universal gate fidelities exceeding an error correction threshold of 99 per cent3. Among the many qubit platforms, only superconducting circuits4, trapped ions5 and nitrogen-vacancy centers in diamond6 have delivered this requirement. Electron spin qubits in silicon7-15 are particularly promising for a large-scale quantum computer owing to their nanofabrication capability, but the two-qubit gate fidelity has been limited to 98 per cent owing to the slow operation16. Here we demonstrate a two-qubit gate fidelity of 99.5 per cent, along with single-qubit gate fidelities of 99.8 per cent, in silicon spin qubits by fast elec. control using a micromagnet-induced gradient field and a tunable two-qubit coupling. We identify the qubit rotation speed and coupling strength where we robustly achieve high-fidelity gates. We realize Deutsch-Jozsa and Grover search algorithms with high success rates using our universal gate set. Our results demonstrate universal gate fidelity beyond the fault-tolerance threshold and may enable scalable silicon quantum computers.
  13. 13
    Xue, X.; Russ, M.; Samkharadze, N.; Undseth, B.; Sammak, A.; Scappucci, G.; Vandersypen, L. M. K. Quantum logic with spin qubits crossing the surface code threshold. Nature 2022, 601, 343,  DOI: 10.1038/s41586-021-04273-w
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    13
    Quantum logic with spin qubits crossing surface code threshold
    Xue, Xiao; Russ, Maximilian; Samkharadze, Nodar; Undseth, Brennan; Sammak, Amir; Scappucci, Giordano; Vandersypen, Lieven M. K.
    Nature (London, United Kingdom) (2022), 601 (7893), 343-347CODEN: NATUAS; ISSN:1476-4687. (Nature Portfolio)
    High-fidelity control of quantum bits is paramount for the reliable execution of quantum algorithms and for achieving fault tolerance-the ability to correct errors faster than they occur1. The central requirement for fault tolerance is expressed in terms of an error threshold. Whereas the actual threshold depends on many details, a common target is the approx. 1% error threshold of the well-known surface code2,3. Reaching two-qubit gate fidelities above 99% has been a long-standing major goal for semiconductor spin qubits. These qubits are promising for scaling, as they can leverage advanced semiconductor technol.4. Here we report a spin-based quantum processor in silicon with single-qubit and two-qubit gate fidelities, all of which are above 99.5%, extd. from gate-set tomog. The av. single-qubit gate fidelities remain above 99% when including crosstalk and idling errors on the neighboring qubit. Using this high-fidelity gate set, we execute the demanding task of calcg. mol. ground-state energies using a variational quantum eigensolver algorithm5. Having surpassed the 99% barrier for the two-qubit gate fidelity, semiconductor qubits are well positioned on the path to fault tolerance and to possible applications in the era of noisy intermediate-scale quantum devices.
  14. 14
    Hendrickx, N. W.; Lawrie, W. I. L.; Russ, M.; van Riggelen, F.; de Snoo, S. L.; Schouten, R. N.; Sammak, A.; Scappucci, G.; Veldhorst, M. A four-qubit germanium quantum processor. Nature 2021, 591, 580,  DOI: 10.1038/s41586-021-03332-6
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    14
    A four-qubit germanium quantum processor
    Hendrickx, Nico W.; Lawrie, William I. L.; Russ, Maximilian; van Riggelen, Floor; de Snoo, Sander L.; Schouten, Raymond N.; Sammak, Amir; Scappucci, Giordano; Veldhorst, Menno
    Nature (London, United Kingdom) (2021), 591 (7851), 580-585CODEN: NATUAS; ISSN:0028-0836. (Nature Research)
    The prospect of building quantum circuits1,2 using advanced semiconductor manufg. makes quantum dots an attractive platform for quantum information processing3,4. Extensive studies of various materials have led to demonstrations of two-qubit logic in gallium arsenide5, silicon6-12 and germanium13. However, interconnecting larger nos. of qubits in semiconductor devices has remained a challenge. Here we demonstrate a four-qubit quantum processor based on hole spins in germanium quantum dots. Furthermore, we define the quantum dots in a two-by-two array and obtain controllable coupling along both directions. Qubit logic is implemented all-elec. and the exchange interaction can be pulsed to freely program one-qubit, two-qubit, three-qubit and four-qubit operations, resulting in a compact and highly connected circuit. We execute a quantum logic circuit that generates a four-qubit Greenberger-Horne-Zeilinger state and we obtain coherent evolution by incorporating dynamical decoupling. These results are a step towards quantum error correction and quantum simulation using quantum dots.
  15. 15
    Philips, S. G. J.; Mądzik, M. T.; Amitonov, S. V.; de Snoo, S. L.; Russ, M.; Kalhor, N.; Volk, C.; Lawrie, W. I. L.; Brousse, D.; Tryputen, L.; Paquelet Wuetz, B.; Sammak, A.; Veldhorst, M.; Scappucci, G.; Vandersypen, L. M. K. Universal control of a six-qubit quantum processor in silicon. Nature 2022, 609, 919– 924,  DOI: 10.1038/s41586-022-05117-x
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    15
    Universal control of a six-qubit quantum processor in silicon
    Philips, Stephan G. J.; Madzik, Mateusz T.; Amitonov, Sergey V.; de Snoo, Sander L.; Russ, Maximilian; Kalhor, Nima; Volk, Christian; Lawrie, William I. L.; Brousse, Delphine; Tryputen, Larysa; Wuetz, Brian Paquelet; Sammak, Amir; Veldhorst, Menno; Scappucci, Giordano; Vandersypen, Lieven M. K.
    Nature (London, United Kingdom) (2022), 609 (7929), 919-924CODEN: NATUAS; ISSN:1476-4687. (Nature Portfolio)
    Future quantum computers capable of solving relevant problems will require a large no. of qubits that can be operated reliably1. However, the requirements of having a large qubit count and operating with high fidelity are typically conflicting. Spins in semiconductor quantum dots show long-term promise2,3 but demonstrations so far use between one and four qubits and typically optimize the fidelity of either single- or two-qubit operations, or initialization and readout4-11. Here, we increase the no. of qubits and simultaneously achieve respectable fidelities for universal operation, state prepn. and measurement. We design, fabricate and operate a six-qubit processor with a focus on careful Hamiltonian engineering, on a high level of abstraction to program the quantum circuits, and on efficient background calibration, all of which are essential to achieve high fidelities on this extended system. State prepn. combines initialization by measurement and real-time feedback with quantum-non-demolition measurements. These advances will enable testing of increasingly meaningful quantum protocols and constitute a major stepping stone towards large-scale quantum computers.
  16. 16
    Petit, L.; Eenink, H. G. J.; Russ, M.; Lawrie, W. I. L.; Hendrickx, N. W.; Phillips, S. G. J.; Clarke, J. S.; Vandersypen, L. M. K.; Veldhorst, M. Universal quantum logic in hot silicon qubits. Nature 2020, 580, 355,  DOI: 10.1038/s41586-020-2170-7
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    16
    Universal quantum logic in hot silicon qubits
    Petit, L.; Eenink, H. G. J.; Russ, M.; Lawrie, W. I. L.; Hendrickx, N. W.; Philips, S. G. J.; Clarke, J. S.; Vandersypen, L. M. K.; Veldhorst, M.
    Nature (London, United Kingdom) (2020), 580 (7803), 355-359CODEN: NATUAS; ISSN:0028-0836. (Nature Research)
    Quantum computation requires many qubits that can be coherently controlled and coupled to each other. Qubits that are defined using lithog. techniques have been suggested to enable the development of scalable quantum systems because they can be implemented using semiconductor fabrication technol. However, leading solid-state approaches function only at temps. below 100 mK, where cooling power is extremely limited, and this severely affects the prospects of practical quantum computation. Recent studies of electron spins in silicon have made progress towards a platform that can be operated at higher temps. by demonstrating long spin lifetimes, gate-based spin readout and coherent single-spin control. However, a high-temp. two-qubit logic gate has not yet been demonstrated. Here, the authors show that silicon quantum dots can have sufficient thermal robustness to enable the execution of a universal gate set at temps. greater than one kelvin. They obtain single-qubit control via ESR and readout using Pauli spin blockade. In addn., they show individual coherent control of two qubits and measure single-qubit fidelities of up to 99.3%. They demonstrate the tunability of the exchange interaction between the two spins from 0.5 to 18 MHz and use it to execute coherent two-qubit controlled rotations. The demonstration of 'hot' and universal quantum logic in a semiconductor platform paves the way for quantum integrated circuits that host both the quantum hardware and its control circuitry on the same chip, providing a scalable approach towards practical quantum information processing.
  17. 17
    Yang, C. H.; Leon, R. C. C.; Hwang, J. C. C.; Saraiva, A.; Tanttu, T.; Huang, W.; Camirand Lemyre, J.; Chan, K. W.; Tan, K. Y.; Hudson, F. E.; Itoh, K. M.; Morello, A.; Pioro-Ladrière, M.; Laucht, A.; Dzurak, A. S. Operation of a silicon quantum processor unit cell above one kelvin. Nature 2020, 580, 350,  DOI: 10.1038/s41586-020-2171-6
    Google Scholar
    17
    Operation of a silicon quantum processor unit cell above one kelvin
    Yang, C. H.; Leon, R. C. C.; Hwang, J. C. C.; Saraiva, A.; Tanttu, T.; Huang, W.; Camirand Lemyre, J.; Chan, K. W.; Tan, K. Y.; Hudson, F. E.; Itoh, K. M.; Morello, A.; Pioro-Ladriere, M.; Laucht, A.; Dzurak, A. S.
    Nature (London, United Kingdom) (2020), 580 (7803), 350-354CODEN: NATUAS; ISSN:0028-0836. (Nature Research)
    Abstr.: Quantum computers are expected to outperform conventional computers in several important applications, from mol. simulation to search algorithms, once they can be scaled up to large nos.-typically millions-of quantum bits (qubits)1-3. For most solid-state qubit technologies-for example, those using superconducting circuits or semiconductor spins-scaling poses a considerable challenge because every addnl. qubit increases the heat generated, whereas the cooling power of diln. refrigerators is severely limited at their operating temp. (less than 100 mK)4-6. Here we demonstrate the operation of a scalable silicon quantum processor unit cell comprising two qubits confined to quantum dots at about 1.5 K. We achieve this by isolating the quantum dots from the electron reservoir, and then initializing and reading the qubits solely via tunnelling of electrons between the two quantum dots7-9. We coherently control the qubits using elec. driven spin resonance10,11 in isotopically enriched silicon1228Si, attaining single-qubit gate fidelities of 98.6 per cent and a coherence time of 2μs during 'hot' operation, comparable to those of spin qubits in natural silicon at millikelvin temps.13-16. Furthermore, we show that the unit cell can be operated at magnetic fields as low as 0.1 T, corresponding to a qubit control frequency of 3.5 GHz, where the qubit energy is well below the thermal energy. The unit cell constitutes the core building block of a full-scale silicon quantum computer and satisfies layout constraints required by error-correction architectures8,17. Our work indicates that a spin-based quantum computer could be operated at increased temps. in a simple pumped 4He system (which provides cooling power orders of magnitude higher than that of diln. refrigerators), thus potentially enabling the integration of classical control electronics with the qubit array18,19.
  18. 18
    Camenzind, L. C.; Geyer, S.; Fuhrer, A.; Warburton, R. J.; Zumbühl, D. M.; Kuhlmann, A. V. A hole spin qubit in a fin field-effect transistor above 4 Kelvin. Nature Electronics 2022, 5, 178,  DOI: 10.1038/s41928-022-00722-0
    Google Scholar
    There is no corresponding record for this reference.
  19. 19
    Ansaloni, F.; Chatterjee, A.; Bohuslavskyi, H.; Bertrand, B.; Hutin, L.; Vinet, M.; Kuemmeth, F. Single-electron operations in a foundry-fabricated array of quantum dots. Nat. Commun. 2020, 11, 6399,  DOI: 10.1038/s41467-020-20280-3
    Google Scholar
    19
    Single-electron operations in a foundry-fabricated array of quantum dots
    Ansaloni, Fabio; Chatterjee, Anasua; Bohuslavskyi, Heorhii; Bertrand, Benoit; Hutin, Louis; Vinet, Maud; Kuemmeth, Ferdinand
    Nature Communications (2020), 11 (1), 6399CODEN: NCAOBW; ISSN:2041-1723. (Nature Research)
    Silicon quantum dots are attractive for the implementation of large spin-based quantum processors in part due to prospects of industrial foundry fabrication. However, the large effective mass assocd. with electrons in silicon traditionally limits single-electron operations to devices fabricated in customized academic clean rooms. Here, we demonstrate single-electron occupations in all four quantum dots of a 2 x 2 split-gate silicon device fabricated entirely by 300-mm-wafer foundry processes. By applying gate-voltage pulses while performing high-frequency reflectometry off one gate electrode, we perform single-electron operations within the array that demonstrate single-shot detection of electron tunneling and an overall adjustability of tunneling times by a global top gate electrode. Lastly, we use the two-dimensional aspect of the quantum dot array to exchange two electrons by spatial permutation, which may find applications in permutation-based quantum algorithms.
  20. 20
    Zwerver, A.-M. J.; Krähenmann, T.; Watson, T. F.; Lampert, L.; George, H. C.; Pillarisetty, R.; Bojarski, S. A.; Amin, P.; Amitonov, S. V.; Boter, J. M.; Caudillo, R.; Corras-Serrano, D.; Dehollain, J. P.; Droulers, G.; Henry, E. M.; Kotlyar, R.; Lodari, M.; Lüthi, F.; Michalak, D. J.; Mueller, B. K.; Neyens, S.; Roberts, J.; Samkharadze, N.; Zheng, G.; Zietz, O. K.; Scappucci, G.; Veldhorst, M.; Vandersypen, L. M. K.; Clarke, J. S. Qubits made by advanced semiconductor manufacturing. Nature Electronics 2022, 5, 184,  DOI: 10.1038/s41928-022-00727-9
    Google Scholar
    There is no corresponding record for this reference.
  21. 21
    Bavdaz, P. L.; Eenink, H. G. J.; van Staveren, J.; Lodari, M.; Almudever, C. G.; Clarke, J. S.; Sebastiano, F.; Veldhorst, M.; Scappucci, G. A quantum dot crossbar with sublinear scaling of interconnects at cryogenic temperature. npj Quantum Information 2022, 8, 86,  DOI: 10.1038/s41534-022-00597-1
    Google Scholar
    There is no corresponding record for this reference.
  22. 22
    Hill, C. D.; Peretz, E.; Hile, S. J.; House, M. G.; Fuechsle, M.; Rogge, S.; Simmons, M. Y.; Hollenberg, L. C. L. A surface code quantum computer in silicon. Science Advances 2015, 1, e1500707  DOI: 10.1126/sciadv.1500707
    Google Scholar
    22
    A surface code quantum computer in silicon
    Hill, Charles D.; Peretz, Eldad; Hile, Samuel J.; House, Matthew G.; Fuechsle, Martin; Rogge, Sven; Simmons, Michelle Y.; Hollenberg, Lloyd C. L.
    Science Advances (2015), 1 (9), e1500707/1-e1500707/11CODEN: SACDAF; ISSN:2375-2548. (American Association for the Advancement of Science)
    The exceptionally long quantum coherence times of phosphorus donor nuclear spin qubits in silicon, coupled with the proven scalability of silicon-based nano-electronics, make them attractive candidates for large-scale quantum computing. However, the high threshold of topol. quantum error correction can only be captured in a two-dimensional array of qubits operating synchronously and in parallel-posing formidable fabrication and control challenges. We present an architecture that addresses these problems through a novel shared-control paradigm that is particularly suited to the natural uniformity of the phosphorus donor nuclear spin qubit states and electronic confinement. The architecture comprises a two-dimensional lattice of donor qubits sandwiched between two vertically sepd. control layers forming a mutually perpendicular crisscross gate array. Shared-control lines facilitate loading/unloading of single electrons to specific donors, thereby activating multiple qubits in parallel across the array on which the required operations for surface code quantum error correction are carried out by global spin control. The complexities of independent qubit control, wave function engineering, and ad hoc quantum interconnects are explicitly avoided. With many of the basic elements of fabrication and control based on demonstrated techniques and with simulated quantum operation below the surface code error threshold, the architecture represents a new pathway for large-scale quantum information processing in silicon and potentially in other qubit systems where uniformity can be exploited.
  23. 23
    Veldhorst, M.; Eenink, H. G. J.; Yang, C. H.; Dzurak, A. S. Silicon CMOS architecture for a spin-based quantum computer. Nat. Commun. 2017, 8, 1766,  DOI: 10.1038/s41467-017-01905-6
    Google Scholar
    23
    Silicon CMOS architecture for a spin-based quantum computer
    Veldhorst M; Eenink H G J; Veldhorst M; Eenink H G J; Yang C H; Dzurak A S
    Nature communications (2017), 8 (1), 1766 ISSN:.
    Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.
  24. 24
    Li, R.; Petit, L.; Franke, D. P.; Dehollain, J. P.; Helsen, J.; Steudtner, M.; Thomas, N. K.; Yoscovits, Z. R.; Singh, K. J.; Wehner, S.; Vandersypen, L. M. K.; Clarke, J. S.; Veldhorst, M. A crossbar network for silicon quantum dot qubits. Science Advances 2018, 4, eaar3960  DOI: 10.1126/sciadv.aar3960
    Google Scholar
    There is no corresponding record for this reference.
  25. 25
    Thorbeck, T.; Zimmerman, N. M. Formation of strain-induced quantum dots in gated semiconductor nanostructures. AIP Advances 2015, 5, 087107,  DOI: 10.1063/1.4928320
    Google Scholar
    25
    Formation of strain-induced quantum dots in gated semiconductor nanostructures
    Thorbeck, Ted; Zimmerman, Neil M.
    AIP Advances (2015), 5 (8), 087107/1-087107/10CODEN: AAIDBI; ISSN:2158-3226. (American Institute of Physics)
    A long-standing mystery in the field of semiconductor quantum dots (QDs) is: Why are there so many unintentional dots (also known as disorder dots) which are neither expected nor controllable. It is typically assumed that these unintentional dots are due to charged defects, however the frequency and predictability of the location of the unintentional QDs suggests there might be addnl. mechanisms causing the unintentional QDs besides charged defects. We show that the typical strains in a semiconductor nanostructure from metal gates are large enough to create strain-induced quantum dots. We simulate a commonly used QD device architecture, metal gates on bulk silicon, and show the formation of strain-induced QDs. The strain-induced QD can be eliminated by replacing the metal gates with poly-silicon gates. Thus strain can be as important as electrostatics to QD device operation operation. (c) 2015 American Institute of Physics.
  26. 26
    Stein, R. M.; Barcikowski, Z. S.; Pookpanratana, S. J.; Pomeroy, J. M.; Stewart, M. D., Jr. Alternatives to aluminum gates for silicon quantum devices: Defects and strain. J. Appl. Phys. 2021, 130, 115102,  DOI: 10.1063/5.0061369
    Google Scholar
    26
    Alternatives to aluminum gates for silicon quantum devices: Defects and strain
    Stein, Ryan M.; Barcikowski, Z. S.; Pookpanratana, S. J.; Pomeroy, J. M.; Stewart, M. D.
    Journal of Applied Physics (Melville, NY, United States) (2021), 130 (11), 115102CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)
    Gate-defined quantum dots benefit from the use of small grain size metals for gate materials because they aid in shrinking the device dimensions. However, it is not clear what differences arise with respect to process-induced defect densities and inhomogeneous strain. Here, we present measurements of fixed charge, Qf; interface trap d., Dit; the intrinsic film stress, σ; and the coeff. of thermal expansion, α, as a function of forming gas anneal temp. for Al, Ti/Pd, and Ti/Pt gates. We show that Dit is minimized at an anneal temp. of 350°C for all materials, but Ti/Pd and Ti/Pt have higher Qf and Dit compared to Al. In addn., σ and α increase with anneal temp. for all three metals with α larger than the bulk value. These results indicate that there is a trade-off between minimizing defects and minimizing the impact of strain in quantum device fabrication. (c) 2021 American Institute of Physics.
  27. 27
    Lawrie, W. I. L.; Eenink, H. G. J.; Hendrickx, N. W.; Boter, J. M.; Petit, L.; Amitonov, S. V.; Lodari, M.; Paquelet Wuetz, B.; Volk, C.; Philips, S. G. J.; Droulers, G.; Kalhor, N.; van Riggelen, F.; Brousse, D.; Sammak, A.; Vandersypen, L. M. K.; Scappucci, G.; Veldhorst, M. Quantum dot arrays in silicon and germanium. Appl. Phys. Lett. 2020, 116, 080501,  DOI: 10.1063/5.0002013
    Google Scholar
    27
    Quantum dot arrays in silicon and germanium
    Lawrie, W. I. L.; Eenink, H. G. J.; Hendrickx, N. W.; Boter, J. M.; Petit, L.; Amitonov, S. V.; Lodari, M.; Paquelet Wuetz, B.; Volk, C.; Philips, S. G. J.; Droulers, G.; Kalhor, N.; van Riggelen, F.; Brousse, D.; Sammak, A.; Vandersypen, L. M. K.; Scappucci, G.; Veldhorst, M.
    Applied Physics Letters (2020), 116 (8), 080501CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
    Electrons and holes confined in quantum dots define excellent building blocks for quantum emergence, simulation, and computation. Silicon and germanium are compatible with std. semiconductor manufg. and contain stable isotopes with zero nuclear spin, thereby serving as excellent hosts for spins with long quantum coherence. Here, we demonstrate quantum dot arrays in a silicon metal-oxide-semiconductor (SiMOS), strained silicon (Si/SiGe), and strained germanium (Ge/SiGe). We fabricate using a multi-layer technique to achieve tightly confined quantum dots and compare integration processes. While SiMOS can benefit from a larger temp. budget and Ge/SiGe can make an Ohmic contact to metals, the overlapping gate structure to define the quantum dots can be based on a nearly identical integration. We realize charge sensing in each platform, for the first time in Ge/SiGe, and demonstrate fully functional linear and two-dimensional arrays where all quantum dots can be depleted to the last charge state. In Si/SiGe, we tune a quintuple quantum dot using the N + 1 method to simultaneously reach the few electron regime for each quantum dot. We compare capacitive crosstalk and find it to be the smallest in SiMOS, relevant for the tuning of quantum dot arrays. We put these results into perspective for quantum technol. and identify industrial qubits, hybrid technol., automated tuning, and two-dimensional qubit arrays as four key trajectories that, when combined, enable fault-tolerant quantum computation. (c) 2020 American Institute of Physics.
  28. 28
    Borsoi, F.; Hendrickx, N. W.; John, V.; Motz, S.; van Riggelen, F.; Sammak, A.; de Snoo, S. L.; Scappucci, G.; Veldhorst, M. Shared control of a 16 semiconductor quantum dot crossbar array. arXiv, 2209.06609 (2022).
    Google Scholar
    There is no corresponding record for this reference.
  29. 29
    Zajac, D. M.; Hazard, T. M.; Mi, X.; Nielsen, E.; Petta, J. R. Scalable gate architecture for a one-dimensional array of semiconductor spin qubits. Physical Review Applied 2016, 6, 054013,  DOI: 10.1103/PhysRevApplied.6.054013
    Google Scholar
    29
    Scalable gate architecture for a one-dimensional array of semiconductor spin qubits
    Zajac, D. M.; Hazard, T. M.; Mi, X.; Nielsen, E.; Petta, J. R.
    Physical Review Applied (2016), 6 (5), 054013/1-054013/8CODEN: PRAHB2; ISSN:2331-7019. (American Physical Society)
    We demonstrate a 12-quantum-dot device fabricated on an undoped Si/SiGe heterostructure as a proof of concept for a scalable, linear gate architecture for semiconductor quantum dots. The device consists of nine quantum dots in a linear array and three single-quantum-dot charge sensors. We show reproducible single-quantum-dot charging and orbital energies, with std. deviations less than 20% relative to the mean across the nine-dot array. The single-quantum-dot charge sensors have a charge sensitivity of 8.2 × 10-4 e/ √HZ and allow for the investigation of real-time charge dynamics. As a demonstration of the versatility of this device, we use single-shot readout to measure the spin-relaxation time T1 170 ms at a magnetic field B =1 T. By reconfiguring the device, we form two capacitively coupled double quantum dots and ext. a mutual charging energy of 200 μeV, which indicates that 50-GHz two-qubit gate-operation speeds are feasible.
  30. 30
    Mills, A. R.; Zajac, D. M.; Gullans, M. J.; Schupp, F. J.; Hazard, T. M.; Petta, J. R. Shuttling a single charge across a one-dimensional array of silicon quantum dots. Nat. Commun. 2019, 10, 1063,  DOI: 10.1038/s41467-019-08970-z
    Google Scholar
    30
    Shuttling a single charge across a one-dimensional array of silicon quantum dots
    Mills A R; Zajac D M; Gullans M J; Schupp F J; Hazard T M; Petta J R
    Nature communications (2019), 10 (1), 1063 ISSN:.
    Significant advances have been made towards fault-tolerant operation of silicon spin qubits, with single qubit fidelities exceeding 99.9%, several demonstrations of two-qubit gates based on exchange coupling, and the achievement of coherent single spin-photon coupling. Coupling arbitrary pairs of spatially separated qubits in a quantum register poses a significant challenge as most qubit systems are constrained to two dimensions with nearest neighbor connectivity. For spins in silicon, new methods for quantum state transfer should be developed to achieve connectivity beyond nearest-neighbor exchange. Here we demonstrate shuttling of a single electron across a linear array of nine series-coupled silicon quantum dots in ~50 ns via a series of pairwise interdot charge transfers. By constructing more complex pulse sequences we perform parallel shuttling of two and three electrons at a time through the array. These experiments demonstrate a scalable approach to physically transporting single electrons across large silicon quantum dot arrays.
  31. 31
    Dodson, J. P.; Holman, N.; Thorgrimsson, B.; Neyens, S. F.; MacQuarrie, E. R.; McJunkin, T.; Foote, R. H.; Edge, L. F.; Coppersmith, S. N.; Eriksson, M. A. Fabrication process and failure analysis for robust quantum dots in silicon. Nanotechnology 2020, 31, 505001,  DOI: 10.1088/1361-6528/abb559
    Google Scholar
    31
    Fabrication process and failure analysis for robust quantum dots in silicon
    Dodson, J. P.; Holman, Nathan; Thorgrimsson, Brandur; Neyens, Samuel F.; MacQuarrie, E. R.; McJunkin, Thomas; Foote, Ryan H.; Edge, L. F.; Coppersmith, S. N.; Eriksson, M. A.
    Nanotechnology (2020), 31 (50), 505001CODEN: NNOTER; ISSN:1361-6528. (IOP Publishing Ltd.)
    We present an improved fabrication process for overlapping aluminum gate quantum dot devices on Si/SiGe heterostructures that incorporates low-temp. inter-gate oxidn., thermal annealing of gate oxide, on-chip electrostatic discharge (ESD) protection and an optimized interconnect process for thermal budget considerations. This process reduces gate-to-gate leakage, damage from ESD, dewetting of aluminum and formation of undesired alloys in device interconnects. Addnl., cross-sectional scanning transmission electron microscopy (STEM) images elucidate gate electrode morphol. in the active region as device geometry is varied. We show that overlapping aluminum gate layers homogeneously conform to the topol. beneath them, independent of gate geometry and identify crit. dimensions in the gate geometry where pattern transfer becomes non-ideal, causing device failure.
  32. 32
    Ha, W.; Ha, S. D.; Choi, M. D.; Tang, Y.; Schmitz, A. E.; Levendorf, M. P.; Lee, K.; Chappell, J. M.; Adams, T. S.; Hulbert, D. R.; Acuna, E.; Noah, R. S.; Matten, J. W.; Jura, M. P.; Wright, J. A.; Rakher, M. T.; Borselli, M. G. A flexible design platform for Si/SiGe exchange-only qubits with low disorder. Nano Lett. 2022, 22, 1443,  DOI: 10.1021/acs.nanolett.1c03026
    Google Scholar
    32
    A Flexible Design Platform for Si/SiGe Exchange-Only Qubits with Low Disorder
    Ha, Wonill; Ha, Sieu D.; Choi, Maxwell D.; Tang, Yan; Schmitz, Adele E.; Levendorf, Mark P.; Lee, Kangmu; Chappell, James M.; Adams, Tower S.; Hulbert, Daniel R.; Acuna, Edwin; Noah, Ramsey S.; Matten, Justine W.; Jura, Michael P.; Wright, Jeffrey A.; Rakher, Matthew T.; Borselli, Matthew G.
    Nano Letters (2022), 22 (3), 1443-1448CODEN: NALEFD; ISSN:1530-6984. (American Chemical Society)
    Spin-based silicon quantum dots are an attractive qubit technol. for quantum information processing with respect to coherence time, control, and engineering. Here we present an exchange-only Si qubit device platform that combines the throughput of CMOS-like wafer processing with the versatility of direct-write lithog. The technol., which we coin "SLEDGE", features dot-shaped gates that are patterned simultaneously on one topog. plane and subsequently connected by vias to interconnect metal lines. The process design enables nontrivial layouts as well as flexibility in gate dimensions, material selection, and addnl. device features such as for rf qubit control. We show that the SLEDGE process has reduced electrostatic disorder with respect to traditional overlapping gate devices with lift-off metalization, and we present spin coherent exchange oscillations and single qubit blind randomized benchmarking data.
  33. 33
    Lu, T. M.; Lee, C.-H.; Huang, S.-H.; Tsui, D. C.; Liu, C. W. Upper limit of two-dimensional electron density in enhancement-mode Si/SiGe heterostructure field-effect transistors. Appl. Phys. Lett. 2011, 99, 153510,  DOI: 10.1063/1.3652909
    Google Scholar
    33
    Upper limit of two-dimensional electron density in enhancement-mode Si/SiGe heterostructure field-effect transistors
    Lu, T. M.; Lee, C.-H.; Huang, S.-H.; Tsui, D. C.; Liu, C. W.
    Applied Physics Letters (2011), 99 (15), 153510/1-153510/3CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
    We present our study of the max. electron d., nmax, accessible via low-temp. transport expts. in enhancement-mode Si/Si1-xGex heterostructure field-effect transistors. Nmax is much higher than the value obtained from self-consistent Schroedinger-Poisson simulations and that nmax can be changed only by changing the Ge concn. in the Si1-xGex barrier layer, not by varying the barrier layer thickness. The discrepancy between expts. and simulations is explained by a non-thermal-equil. tunneling-limited model. (c) 2011 American Institute of Physics.
  34. 34
    Huang, C.-T.; Li, J.-Y.; Chou, K. S.; Sturm, J. C. Screening of remote charge scattering sites from the oxide/silicon interface of strained Si two-dimensional electron gases by an intermediate tunable shielding electron layer. Appl. Phys. Lett. 2014, 104, 243510,  DOI: 10.1063/1.4884650
    Google Scholar
    34
    Screening of remote charge scattering sites from the oxide/silicon interface of strained Si two-dimensional electron gases by an intermediate tunable shielding electron layer
    Huang, Chiao-Ti; Li, Jiun-Yun; Chou, Kevin S.; Sturm, James C.
    Applied Physics Letters (2014), 104 (24), 243510/1-243510/4CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
    We report the strong screening of the remote charge scattering sites from the oxide/semiconductor interface of buried enhancement-mode undoped Si two-dimensional electron gases (2DEGs), by introducing a tunable shielding electron layer between the 2DEG and the scattering sites. When a high d. of electrons in the buried silicon quantum well exists, the tunneling of electrons from the buried layer to the surface quantum well can lead to the formation of a nearly immobile surface electron layer. The screening of the remote charges at the interface by this newly formed surface electron layer results in an increase in the mobility of the buried 2DEG. Furthermore, a significant decrease in the min. mobile electron d. of the 2DEG occurs as well. Together, these effects can reduce the increased detrimental effect of interface charges as the setback distance for the 2DEG to the surface is reduced for improved lateral confinement by top gates. (c) 2014 American Institute of Physics.
  35. 35
    Laroche, D.; Huang, S. H.; Nielsen, E.; Chuang, Y.; Li, J.-Y.; Liu, C. W.; Lu, T. M. Scattering mechanisms in shallow undoped Si/SiGe quantum wells. AIP Advances 2015, 5, 107106,  DOI: 10.1063/1.4933026
    Google Scholar
    35
    Scattering mechanisms in shallow undoped Si/SiGe quantum wells
    Laroche, D.; Huang, S.-H.; Nielsen, E.; Chuang, Y.; Li, J.-Y.; Liu, C. W.; Lu, T. M.
    AIP Advances (2015), 5 (10), 107106/1-107106/10CODEN: AAIDBI; ISSN:2158-3226. (American Institute of Physics)
    We report the magneto-transport study and scattering mechanism anal. of a series of increasingly shallow Si/SiGe quantum wells with depth ranging from ∼ 100 nm to ∼ 10 nm away from the heterostructure surface. The peak mobility increases with depth, suggesting that charge centers near the oxide/semiconductor interface are the dominant scattering source. The power-law exponent of the electron mobility vs. d. curve, μ .varies. nα, is extd. as a function of the depth of the Si quantum well. At intermediate densities, the power-law dependence is characterized by α ∼ 2.3. At the highest achievable densities in the quantum wells buried at intermediate depth, an exponent α ∼ 5 is obsd. We propose and show by simulations that this increase in the mobility dependence on the d. can be explained by a non-equil. model where trapped electrons smooth out the potential landscape seen by the two-dimensional electron gas. (c) 2015 American Institute of Physics.
  36. 36
    Su, Y.-H.; Chuang, Y.; Liu, C.-Y.; Li, J.-Y.; Lu, T.-M. Effects of surface tunneling of two-dimensional hole gases in undoped Ge/GeSi heterostructures. Physical Review Materials 2017, 1, 044601,  DOI: 10.1103/PhysRevMaterials.1.044601
    Google Scholar
    36
    Effects of surface tunneling of two-dimensional hole gases in undoped Ge/GeSi heterostructures
    Su, Yi-Hsin; Chuang, Yen; Liu, Chia-You; Li, Jiun-Yun; Lu, Tzu-Ming
    Physical Review Materials (2017), 1 (4), 044601/1-044601/6CODEN: PRMHBS; ISSN:2475-9953. (American Physical Society)
    We investigate the effect of surface tunneling on charge distributions of two-dimensional hole gases (2DHGs) in undoped Ge/GeSi heterostructures. As in the electron channel case, the 2DHG d. sats. at a high gate voltage. As the channel depth of 2DHGs increases, a crossover of charge distributions in the system from equil. to nonequil. is obsd. at a depth of∼50 nm. A surface tunneling model is proposed to explain the d. crossover. Magnetotransport anal. is performed to investigate the limiting scattering mechanisms. The power law dependence of mobility on d. suggests that the dominant scattering mechanisms for the shallow- and deep-channel 2DHGs are remote impurity and background impurity scattering, resp. Clear quantum Hall plateaus and vanishing longitudinalmagnetoresistance are obsd. in the2DHGdevice of channels as shallow as 9 nm.
  37. 37
    Chou, K.-Y.; Hsu, N.-W.; Su, Y.-H.; Chou, C.-T.; Chiu, P.-Y.; Chuang, Y.; Li, J.-Y. Temperature dependence of dc transport characteristics for a two-dimensional electron gas in an undoped Si/SiGe heterostructure. Appl. Phys. Lett. 2018, 112, 083502,  DOI: 10.1063/1.5018636
    Google Scholar
    37
    Temperature dependence of DC transport characteristics for a two-dimensional electron gas in an undoped Si/SiGe heterostructure
    Chou, Kuan-Yu; Hsu, Nai-Wen; Su, Yi-Hsin; Chou, Chung-Tao; Chiu, Po-Yuan; Chuang, Yen; Li, Jiun-Yun
    Applied Physics Letters (2018), 112 (8), 083502/1-083502/4CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
    We investigate DC characteristics of a two-dimensional electron gas (2DEG) in an undoped Si/SiGe heterostructure and its temp. dependence. An insulated-gate field-effect transistor was fabricated, and transfer characteristics were measured at 4 K-300 K. At low temps. (T < 45 K), source electrons are injected into the buried 2DEG channel first and drain current increases with the gate voltage. By increasing the gate voltage further, the current sats. followed by a neg. transconductance obsd., which can be attributed to electron tunneling from the buried channel to the surface channel. Finally, the drain current is satd. again at large gate biases due to parallel conduction of buried and surface channels. By increasing the temp., an abrupt increase in threshold voltage is obsd. at T ∼ 45 K and it is speculated that neg. charged impurities at the Al2O3/Si interface are responsible for the threshold voltage shift. At T > 45 K, the current satn. and neg. transconductance disappear and the device acts as a normal transistor. (c) 2018 American Institute of Physics.
  38. 38
    Su, Y.-H.; Chou, K.-Y.; Chuang, Y.; Lu, T.-M.; Li, J.-Y. Electron mobility enhancement in an undoped Si/SiGe heterostructure by remote carrier screening. J. Appl. Phys. 2019, 125, 235705,  DOI: 10.1063/1.5094848
    Google Scholar
    38
    Electron mobility enhancement in an undoped Si/SiGe heterostructure by remote carrier screening
    Su, Yi-Hsin; Chou, Kuan-Yu; Chuang, Yen; Lu, Tzu-Ming; Li, Jiun-Yun
    Journal of Applied Physics (Melville, NY, United States) (2019), 125 (23), 235705/1-235705/9CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)
    We investigate the effects of surface tunneling on electrostatics and transport properties of two-dimensional electron gases (2DEGs) in undoped Si/SiGe heterostructures with different 2DEG depths. By varying the gate voltage, four stages of d.-mobility dependence are identified with two d. satn. regimes obsd., which confirms that the system transitions between equil. and nonequil. Mobility is enhanced with an increasing d. at low biases and, counterintuitively, with a decreasing d. at high biases as well. The d. satn. and mobility enhancement can be semiquant. explained by a surface tunneling model in combination with a bilayer screening theory. (c) 2019 American Institute of Physics.
  39. 39
    Degli Esposti, D.; Paquelet Wuetz, B.; Fezzi, V.; Lodari, M.; Sammak, A.; Scappucci, G. Wafer-scale low-disorder 2DEG in 28Si/SiGe without an epitaxial Si cap. Appl. Phys. Lett. 2022, 120, 184003,  DOI: 10.1063/5.0088576
    Google Scholar
    39
    Wafer-scale low-disorder 2DEG in 28Si/SiGe without an epitaxial Si cap
    Degli Esposti, Davide; Paquelet Wuetz, Brian; Fezzi, Viviana; Lodari, Mario; Sammak, Amir; Scappucci, Giordano
    Applied Physics Letters (2022), 120 (18), 184003CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
    We grow 28Si/SiGe heterostructures by reduced-pressure chem. vapor deposition and terminate the stack without an epitaxial Si cap but with an amorphous Si-rich layer obtained by exposing the SiGe barrier to dichlorosilane at 500 °C. As a result,28Si/SiGe heterostructure field-effect transistors feature a sharp semiconductor/dielec. interface and support a two-dimensional electron gas with enhanced and more uniform transport properties across a 100 mm wafer. At T = 1.7 K, we measure a high mean mobility of (1.8±0.5) x 105 cm2/V s and a low mean percolation d. of (9±1) x 1010 cm-2. From the anal. of Shubnikov-de Haas oscillations at T = 190 mK, we obtain a long mean single particle relaxation time of (8.1±0.5) ps, corresponding to a mean quantum mobility and quantum level broadening of (7.5±0.6) x 104 cm2/V s and (40±3)μeV, resp., and a small mean Dingle ratio of (2.3±0.2), indicating reduced scattering from long range impurities and a low-disorder environment for hosting high-performance spin-qubits. (c) 2022 American Institute of Physics.
  40. 40
    Paquelet Wuetz, B.; Losert, M. P.; Koelling, S.; Stehouwer, L. E. A.; Zwerver, A.-M. J.; Philips, S. G. J.; Mądzik, M. T.; Xue, X.; Zheng, G.; Lodari, M.; Amitonov, S. V.; Samkharadze, N.; Sammak, A.; Vandersypen, L. M. K.; Rahman, R.; Coppersmith, S. N.; Moutanabbir, O.; Friesen, M.; Scappucci, G. Atomic fluctuations lifting the energy degeneracy in Si/SiGe quantum dots. Nat. Commun. 2022, 13, 7730,  DOI: 10.1038/s41467-022-35458-0
    Google Scholar
    40
    Atomic fluctuations lifting the energy degeneracy in Si/SiGe quantum dots
    Paquelet Wuetz, Brian; Losert, Merritt P.; Koelling, Sebastian; Stehouwer, Lucas E. A.; Zwerver, Anne-Marije J.; Philips, Stephan G. J.; Madzik, Mateusz T.; Xue, Xiao; Zheng, Guoji; Lodari, Mario; Amitonov, Sergey V.; Samkharadze, Nodar; Sammak, Amir; Vandersypen, Lieven M. K.; Rahman, Rajib; Coppersmith, Susan N.; Moutanabbir, Oussama; Friesen, Mark; Scappucci, Giordano
    Nature Communications (2022), 13 (1), 7730CODEN: NCAOBW; ISSN:2041-1723. (Nature Portfolio)
    Electron spins in Si/SiGe quantum wells suffer from nearly degenerate conduction band valleys, which compete with the spin degree of freedom in the formation of qubits. Despite attempts to enhance the valley energy splitting deterministically, by engineering a sharp interface, valley splitting fluctuations remain a serious problem for qubit uniformity, needed to scale up to large quantum processors. Here, we elucidate and statistically predict the valley splitting by the holistic integration of 3D at.-level properties, theory and transport. We find that the concn. fluctuations of Si and Ge atoms within the 3D landscape of Si/SiGe interfaces can explain the obsd. large spread of valley splitting from measurements on many quantum dot devices. Against the prevailing belief, we propose to boost these random alloy compn. fluctuations by incorporating Ge atoms in the Si quantum well to statistically enhance valley splitting.
  41. 41
    Ershov, M.; Saxena, S.; Karbasi, H.; Winters, S.; Minehane, S.; Babcock, J.; Lindley, R.; Clifton, P.; Redford, M.; Shibkov, A. Dynamic recovery of negative bias temperature instability in p-type metal–oxide–semiconductor field-effect transistors. Appl. Phys. Lett. 2003, 83, 1647,  DOI: 10.1063/1.1604480
    Google Scholar
    41
    Dynamic recovery of negative bias temperature instability in p-type metal-oxide-semiconductor field-effect transistors
    Ershov, M.; Saxena, S.; Karbasi, H.; Winters, S.; Minehane, S.; Babcock, J.; Lindley, R.; Clifton, P.; Redford, M.; Shibkov, A.
    Applied Physics Letters (2003), 83 (8), 1647-1649CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
    An unexpected phys. phenomenon - dynamic recovery of neg. bias temp. instability (NBTI) - is reported. NBTI degrdn. in p-type MOSFET transistors is significantly (by ∼40%) reduced after stress interruption. NBTI recovery dynamics includes a very fast transient (seconds time scale) followed by a slow (tens of minutes) transient, which tends to sat. Under subsequent application of stress bias, the degrdn. quickly returns to its previous state. Thus, apparent NBTI degrdn. includes permanent and reversible components. NBTI degrdn. and device lifetime depend strongly on the measurement procedure and equipment due to these relaxation phenomena, which should be taken into account in analyzing the results of NBTI measurements.
  42. 42
    Kaczer, B.; Grasser, T.; Roussel, J.; J., Martin-Martinez; R., O’Connor; O’Sullivan, B. J.; Groeseneken, G. Ubiquitous relaxation in BTI stressing─new evaluation and insights, in 2008 IEEE International Reliability Physics Symposium , 2008; pp 20– 27.
    Google Scholar
    There is no corresponding record for this reference.
  43. 43
    Lelis, A. J.; Green, R.; Habersat, D. B.; El, M. Basic mechanisms of threshold-voltage instability and implications for reliability testing of SiC MOSFETs. IEEE Trans. Electron Devices 2015, 62, 316,  DOI: 10.1109/TED.2014.2356172
    Google Scholar
    43
    Basic mechanisms of threshold-voltage instability and implications for reliability testing of SiC MOSFETs
    Lelis, Aivars J.; Green, Ron; Habersat, Daniel B.; El, Mooro
    IEEE Transactions on Electron Devices (2015), 62 (2), 316CODEN: IETDAI; ISSN:0018-9383. (Institute of Electrical and Electronics Engineers)
    A review of the basic mechanisms affecting the stability of the threshold voltage in response to a bias-temp. stress is presented in terms of the charging and activation of near-interfacial oxide traps. An activation energy of approx. 1.1 eV was calcd. based on new exptl. results. Implications of these factors, including the recovery of some bias-temp. stress-activated defects, for improved device reliability testing are discussed.
  44. 44
    Franco, J.; Alian, A.; Kaczer, B.; Lin, D.; Ivanov, T.; Pourghaderi, A.; Martens, K.; Mols, Y.; Zhou, D.; Waldron, N.; Sioncke, S.; Kauerauf, T.; Collaert, N.; Thean, A.; Heyns, M.; Groeseneken, G. Suitability of high-k gate oxides for III–V devices: A PBTI study in In0.53Ga0.47As devices with Al2O3, in 2014 IEEE International Reliability Physics Symposium , 2014; pp 6A.2.1– 6A.2.6.
    Google Scholar
    There is no corresponding record for this reference.
  45. 45
    Neyens, S. F.; MacQuarrie, E. R.; Dodson, J. P.; Corrigan, J.; Holman, N.; Thorgrimsson, B.; Palma, M.; McJunkin, T.; Edge, L. F.; Friesen, M.; Coppersmith, S. N.; Eriksson, M. A. Measurements of capacitive coupling within a quadruple-quantum-dot array. Physical Review Applied 2019, 12, 064049,  DOI: 10.1103/PhysRevApplied.12.064049
    Google Scholar
    45
    Measurements of Capacitive Coupling Within a Quadruple-Quantum-Dot Array
    Neyens, Samuel F.; MacQuarrie, E. R.; Dodson, J. P.; Corrigan, J.; Holman, Nathan; Thorgrimsson, Brandur; Palma, M.; McJunkin, Thomas; Edge, L. F.; Friesen, Mark; Coppersmith, S. N.; Eriksson, M. A.
    Physical Review Applied (2019), 12 (6), 064049CODEN: PRAHB2; ISSN:2331-7019. (American Physical Society)
    We present measurements of the capacitive coupling energy and the interdot capacitances in a linear quadruple-quantum-dot array in undoped Si/SiGe. With the device tuned to a regime of strong (>1GHz) intra-double-dot tunnel coupling, as is typical for double-dot qubits, we measure a capacitive coupling energy of 20.9±0.3GHz. In this regime, we demonstrate a fitting procedure to ext. all the parameters in the four-dimensional Hamiltonian for two capacitively coupled charge qubits from a two-dimensional slice through the quadruple-dot charge-stability diagram. We also investigate the tunability of the capacitive coupling energy, using interdot barrier gate voltages to tune the inter- and intra-double-dot capacitances, and change the capacitive coupling energy of the double dots over a range of 15-32 GHz. We provide a model for the capacitive coupling energy based on the electrostatics of a network of charge nodes joined by capacitors, which shows how the coupling energy should depend on inter-double-dot and intra-double-dot capacitances in the network, and find that the expected trends agree well with the measurements of coupling energy.
  46. 46
    Takeda, K.; Noiri, A.; Nakajima, T.; Yoneda, J.; Kobayashi, T.; Tarucha, S. Quantum tomography of an entangled three-qubit state in silicon. Nat. Nanotechnol. 2021, 16, 965,  DOI: 10.1038/s41565-021-00925-0
    Google Scholar
    46
    Quantum tomography of an entangled three-qubit state in silicon
    Takeda, Kenta; Noiri, Akito; Nakajima, Takashi; Yoneda, Jun; Kobayashi, Takashi; Tarucha, Seigo
    Nature Nanotechnology (2021), 16 (9), 965-969CODEN: NNAABX; ISSN:1748-3387. (Nature Portfolio)
    Quantum entanglement is a fundamental property of coherent quantum states and an essential resource for quantum computing1. In large-scale quantum systems, the error accumulation requires concepts for quantum error correction. A first step toward error correction is the creation of genuinely multipartite entanglement, which has served as a performance benchmark for quantum computing platforms such as superconducting circuits2,3, trapped ions4 and nitrogen-vacancy centers in diamond5. Among the candidates for large-scale quantum computing devices, silicon-based spin qubits offer an outstanding nanofabrication capability for scaling-up. Recent studies demonstrated improved coherence times6-8, high-fidelity all-elec. control9-13, high-temp. operation14,15 and quantum entanglement of two spin qubits9,11,12. Here we generated a three-qubit Greenberger-Horne-Zeilinger state using a low-disorder, fully controllable array of three spin qubits in silicon. We performed quantum state tomog.16 and obtained a state fidelity of 88.0%. The measurements witness a genuine Greenberger-Horne-Zeilinger class quantum entanglement that cannot be sepd. into any biseparable state. Our results showcase the potential of silicon-based spin qubit platforms for multiqubit quantum algorithms.
  47. 47
    Goetzberger, A.; Heine, V.; Nicollian, E. H. Surface states in silicon from charge in the oxide coating. Appl. Phys. Lett. 1968, 12, 95,  DOI: 10.1063/1.1651913
    Google Scholar
    47
    Surface states in silicon from charges in the oxide coating
    Goetzberger, Adolf; Heine, Volker; Nicollian, Edward H.
    Applied Physics Letters (1968), 12 (3), 95-7CODEN: APPLAB; ISSN:0003-6951.
    The exptl. observed distribution of surface state d. vs. energy is correlated with the existence of Coulombic centers in the oxide. Such charges induce peaks in surface state d. near the band edges; deeper levels are introduced by 2 charges in close proximity. 13 references.
  48. 48
    Poindexter, E. H.; Caplan, P. J. Electron spin resonance of inherent and process induced defects near the Si/SiO2 interface of oxidized silicon wafers. Journal of Vacuum Science & Technology A 1988, 6, 1352,  DOI: 10.1116/1.575701
    Google Scholar
    48
    Electron spin resonance of inherent and process induced defects near the silicon/silica interface of oxidized silicon wafers
    Poindexter, Edward H.; Caplan, Philip J.
    Journal of Vacuum Science & Technology, A: Vacuum, Surfaces, and Films (1988), 6 (3, Pt. 2), 1352-7CODEN: JVTAD6; ISSN:0734-2101.
    Major point defects, inherent and process induced, near the Si/SiO2 interface of MOS structures were identified by ESR. The most pervasive defect is the Pb center, a trivalent Si atom bonded to the Si at the interface, with dangling orbital aimed into the SiO2 (e.g., Si≡Si3). The Pb orbital is the source of ∼1/2 of the elec. interface traps (d. Dit) in as-oxidized or radiation- or injection-damaged Si. Concn. of Pb is dependent on oxidn. and other thermal treatments, and is a sensitive gauge of interface physicochem. disposition. Radiationlike processing methods 〈ion implantation, rapid thermal annealing, plasma etching, and electron-beam lithog.〉 generate addnl. point defects, including charged E' centers (O3≡Si•...+Si≡O3), nonbridging oxygen hole centers O3≡Si-O•...H-O-Si≡O3), peroxy radicals (O3≡Si-O-O•...Si≡O3) in the oxide, and D centers (•Si≡Si3)n in the Si. Subsequent thermochem. treatments yield results similar to those obsd. for bulk fused SiO2 defects, but with some unresolved differences. The stability or hardness of Si/SiO2 devices appears to be related to initial defects, despite apparent anneal by thermal processing stages. A no. of studies to define the detailed physicochem. behavior of these potentially troublesome defects are now in progress.
  49. 49
    Lenahan, P. M.; Conley, J. F., Jr. What can electron paramagnetic resonance tell us about the Si/SiO2 system?. Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 1998, 16, 2134,  DOI: 10.1116/1.590301
    Google Scholar
    There is no corresponding record for this reference.
  50. 50
    Stesmans, A.; Nguyen Hoang, T.; Afanas’ev, V. V. Hydrogen interaction kinetics of Ge dangling bonds at the Si0.25Ge0.75/SiO2 interface. J. Appl. Phys. 2014, 116, 044501,  DOI: 10.1063/1.4880739
    Google Scholar
    50
    Hydrogen interaction kinetics of Ge dangling bonds at the Si0.25Ge0.75/SiO2 interface
    Stesmans, A.; Nguyen Hoang, T.; Afanas'ev, V. V.
    Journal of Applied Physics (Melville, NY, United States) (2014), 116 (4), 044501/1-044501/16CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)
    The hydrogen interaction kinetics of the GePb1 defect, previously identified by ESR as an interfacial Ge dangling bond (DB) defect occurring in densities ∼7 × 1012 cm-2 at the SiGe/SiO2 interfaces of condensation grown (100)Si/a-SiO2/Ge0.75Si0.25/a-SiO2 structures, was studied as function of temp. This was carried out, both in the isothermal and isochronal mode, through defect monitoring by capacitance-voltage measurements in conjunction with ESR probing, where it was previously demonstrated the defects to operate as neg. charge traps. The work entails a full interaction cycle study, comprised of anal. of both defect passivation (pictured as GePb1-H formation) in mol. hydrogen (∼1 atm) and reactivation (GePb1-H dissocn.) in vacuum. Both processes can be suitably described sep. by the generalized simple thermal (GST) model, embodying a 1st order interaction kinetics description based on the basic chem. reactions GePb1 + H2 → GePb1H + H and GePb1H → GePb1 + H, which are characterized by the av. activation energies Ef = 1.44 ± 0.04 eV and Ed = 2.23 ± 0.04 eV, and attendant, assumedly Gaussian, spreads σEf = 0.20 ± 0.02 eV and σEd = 0.15 ± 0.02 eV, resp. The substantial spreads refer to enhanced interfacial disorder. Combination of the sep. inferred kinetic parameters for passivation and dissocn. results in the unified realistic GST description that incorporates the simultaneous competing action of passivation and dissocn., and which is found to excellently account for the full cycle data. For process times ta ∼ 35 min, even for the optimum treatment temp. ∼380°, only ∼60% of the GePb1 system can be elec. silenced, still far remote from device grade level. This ineffectiveness is concluded, for the major part, to be a direct consequence of the excessive spreads in the activation energies, ∼2-3 times larger than for the Si DB Pb defects at the std. thermal (111)Si/SiO2 interface which may be easily passivated to device grade levels, strengthened by the reduced difference between the av. Ef and Ed values. Exploring the guidelines of the GST model indicates that passivation can be improved by decreasing Tan and attendant enlarging of ta, however, at best still leaving ∼2% defects unpassivated even for unrealistically extended anneal times. The av. dissocn. energy Ed ∼ 2.23 eV, concluded as representing the GePb1-H bond strength, is smaller than the SiPb-H one, characterized by Ed ∼ 2.83 eV. An energy deficiency is encountered regarding the energy sum rule inherent to the GST-model, the origin of which is substantiated to lie with a more complex nature of the forward passivation process than basically depicted in the GST model. The results are discussed within the context of theor. considerations on the passivation of interfacial Ge DBs by hydrogen. (c) 2014 American Institute of Physics.
  51. 51
    Kerber, A.; Cartier, E.; Groeseneken, G.; Maes, H. E.; Schwalke, U. Stress induced charge trapping effects in SiO2/Al2O3 gate stacks with TiN electrodes. J. Appl. Phys. 2003, 94, 6627,  DOI: 10.1063/1.1621718
    Google Scholar
    51
    Stress-induced charge trapping effects in SiO2/Al2O3 gate stacks with TiN electrodes
    Kerber, A.; Cartier, E.; Groeseneken, G.; Maes, H. E.; Schwalke, U.
    Journal of Applied Physics (2003), 94 (10), 6627-6630CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)
    Strong polarity dependent charge trapping effects have been obsd. in as-deposited SiO2/Al2O3 gate stacks with TiN gate electrodes on n- and p-type Si substrates using current-voltage (I-V) and capacitance-voltage (C-V) sensing techniques. For substrate injection, electron trapping occurs mainly in the bulk of the Al2O3, resulting in pos. voltage shifts for both I-V and C-V measurements. In the case of gate injection, pos. charge trapping near the SiO2/Al2O3 interface leads to neg. voltage shifts for C-V and pos. shifts for I-V measurements. The polarity-dependent charging effects are explained in terms of the difference in barrier height for substrate and gate injection and of the inherent asymmetry of the dual layer gate dielec.
  52. 52
    Pioro-Ladrière, M.; Davies, J. H.; Long, A. R.; Sachrajda, A. S.; Gaudreau, L.; Zawadzki, P.; Lapointe, J.; Gupta, J.; Wasilewski, Z.; Studenikin, S. Origin of switching noise in GaAsAlx/Ga1-xAs lateral gated devices. Phys. Rev. B 2005, 72, 115331,  DOI: 10.1103/PhysRevB.72.115331
    Google Scholar
    52
    Origin of switching noise in GaAs/AlxGa1-xAs lateral gated devices
    Pioro-Ladriere, M.; Davies, John H.; Long, A. R.; Sachrajda, A. S.; Gaudreau, Louis; Zawadzki, P.; Lapointe, J.; Gupta, J.; Wasilewski, Z.; Studenikin, S.
    Physical Review B: Condensed Matter and Materials Physics (2005), 72 (11), 115331/1-115331/8CODEN: PRBMDO; ISSN:1098-0121. (American Physical Society)
    We have studied switching (telegraph) noise at low temp. in GaAs/AlxGa1-xAs heterostructures with lateral gates and introduced a model for its origin, which explains why noise can be suppressed by cooling samples with a pos. bias on the gates. The noise was measured by monitoring the conductance fluctuations around e2/h on the first step of a quantum point contact at around 1.2 K. Cooling with a pos. bias on the gates dramatically reduces this noise, while an asym. bias exacerbates it. Our model is that the noise originates from a leakage current of electrons that tunnel through the Schottky barrier under the gate into the conduction band and become trapped near the active region of the device. The key to reducing noise is to keep the barrier opaque under exptl. conditions. Cooling with a pos. bias on the gates reduces the d. of ionized donors. This builds in an effective neg. gate voltage so that a smaller neg. bias is needed to reach the desired operating point. This suppresses tunneling from the gate and hence the noise. The redn. in the d. of ionized donors also strengthens the barrier to tunneling at a given applied voltage. Further support for the model comes from our direct observation of the leakage current into a closed quantum dot, around 10-20 A for this device. The current was detected by a neighboring quantum point contact, which showed monotonic steps in time assocd. with the tunneling of single electrons into the dot. If asym. gate voltages are applied, our model suggests that the noise will increase as a consequence of the more neg. gate voltage applied to one of the gates to maintain the same device conductance. We observe exactly this behavior in our expts.
  53. 53
    Sze, S. M.; Ng, K. K. Physics of Semiconductor Devices; Wiley: 2006; pp 484– 486.
    Google Scholar
    There is no corresponding record for this reference.
  54. 54
    Vanheusden, K.; Warren, W. L.; Fleetwood, D. M.; Schwank, J. R.; Shaneyfelt, M. R.; Draper, B. L.; Winokur, P. S.; Devine, R. A. B.; Archer, L. B.; Brown, G. A.; Wallace, R. M. Chemical kinetics of mobile-proton generation and annihilation in SiO2 thin films. Appl. Phys. Lett. 1998, 73, 674,  DOI: 10.1063/1.121944
    Google Scholar
    54
    Chemical kinetics of mobile-proton generation and annihilation in SiO2 thin films
    Vanheusden, K.; Warren, W. L.; Fleetwood, D. M.; Schwank, J. R.; Shaneyfelt, M. R.; Draper, B. L.; Winokur, P. S.; Devine, R. A. B.; Archer, L. B.; Brown, G. A.; Wallace, R. M.
    Applied Physics Letters (1998), 73 (5), 674-676CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
    The chem. kinetics of mobile-proton reactions in the SiO2 film of Si/SiO2/Si structures were analyzed as a function of forming-gas anneal parameters in the 300-600° temp. range. The authors' data show that the initial buildup of mobile protons is limited by the rate of lateral H diffusion into the SiO2 films. The final d. of mobile protons is detd. by the cooling rate which terminates the annealing process and, in the case of subsequent anneals, by the temp. of the final anneal. To explain the observations, the authors propose a dynamical equil. model which assumes a reversible interfacial reaction with a temp.-dependent balance.
  55. 55
    Hoffmann, K. System Integration: From Transistor Design to Large Scale Integrated Circuits; Wiley: 2004; pp 339– 340 and 345– 352.
    Google Scholar
    There is no corresponding record for this reference.
  56. 56
    Meyer, M.; Déprez, C.; van Abswoude, T. R.; Meijer, I. N.; Liu, D.; Wang, C.; Karwal, S.; Oosterhout, S.; Borsoi, F.; Sammak, A.; Hendrickx, N. W.; Scappucci, G.; Veldhorst, M. Dataset underlying the manuscript: Electrical control of uniformity in quantum dot devices. Zenodo.org , 2022.
    Google Scholar
    There is no corresponding record for this reference.

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  • Abstract

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    Figure 1

    Figure 1. Fluctuations in the potential landscape in semiconductor quantum dot devices. (a) Schematic of typical semiconductor heterostructures with buried quantum wells studied. The metallic gate electrodes colored in yellow and blue represent the barrier (B) and plunger gates (P) of a quantum dot array, respectively. (b) Potential landscape in an ideal device with shared gate control. The application of the same voltage VP/B on all plunger/barrier gates leads to a regular potential landscape with negligible fluctuations compared to those of the other relevant energy scales (α denotes the gate lever arm). The quantum dots all have the same charge configuration. (c) Potential landscape in state-of-the-art devices with shared gate control. The application of the same voltage VP/B on all plunger/barrier gates leads to an irregular potential landscape due to local fluctuations, which are often comparable to or larger than the charging energy EC. Consequently, the quantum dots have different charge configurations. (d) Typical variations in the pinch-off characteristic of the plunger gates in a state-of-the-art linear quantum dot array (device A), nominally identical with that displayed in in Figure 4a, just after a cooldown. The pinch-off voltage Vthres is defined as the gate voltage for which the current reaches Ithres = 50 pA at a bias of |Vsd| = 100 μV. Here, the pinch-off voltages spread over a voltage range ΔVthres = 226 mV.

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    Figure 2

    Figure 2. Hysteresis of the pinch-off characteristics. (a) Schematics of the measurement sequence used to probe the hysteretic behavior of the pinch-off voltage Vthres of a single gate. Vthres, i.e. the voltage when the current reaches Ithres = 50 pA at a bias voltage |Vsd| = 100 μV, is measured after application of successive stress voltages Vstress for tstress = 1 min. The measurements start with decreasing Vstress. Upon reaching Vstress = Vstressrev, the direction is reversed and a sequence of increasing Vstress is applied. (b) Evolution of the pinch-off voltage Vthres of the sensor plunger gate S1 as a function of the stress voltage Vstress for two different cooldowns of device B. The measurement cycle is sketched in the top illustration. The square and the circle mark the starting point and the ending point of the cycles, respectively. The star indicates the point Vstressrev where the stress voltage sequence is reversed. Vstress is first decreased before being increased again after Vstressrev = −3.7 V. Both sets of points draw hysteresis cycles which overlap. The remaining gates that are needed to form a conductive channel are set to V0 = 1.2 V. (c) (Vstress, Vthres) hysteresis cycles measured successively for plunger gate P1 in device A. The points where the stress voltage sequences are reversed (stars) and ended (circles) are changed between each cycle. Note that for the fifth iteration, the stress voltage sequence with increasing Vstress was stopped purposely when Vthres ≃ 1 V. All other gates were set to V0 = 1.704 V.

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    Figure 3

    Figure 3. Stability of the pinch-off voltage after tuning. (a) Schematic representation of the procedure used to probe the time stability of the pinch-off voltage of a single gate. The gate voltage is continuously swept back and forth to detect the voltage range [Vthres−(t),Vthres+(t)] over which the current stays between Ithres – ΔI and Ithres + ΔI with ΔI ∈ {10 pA, 25 pA}. From each sweep Vthres(t) is extracted by linear regression. (b) Time evolution of Vthres prior to any application of stress voltages (dark pink) and after tuning via application of increasing Vstress with Vstressrev > 0 V (light pink) or decreasing Vstress with Vstressrev < 0 V (violet and blue). The curves are obtained for sensor plunger gate S in device C, except for the pink curve which is obtained for sensor plunger gate S in device D. Ithres = 50 pA, except for the blue curve of decreasing stress, where it was defined as Ithres = 30 pA, which provided a more robust analysis. (c) Relative variations ΔVthres(t) = Vthres(t) – Vthres(t = 3 h) of the data shown in (b).

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    Figure 4

    Figure 4. Homogenization of the potential landscape below the plunger gates of a linear quantum dot array. (a) Scanning electron micrograph of a linear quantum dot array. The plunger, barrier, accumulation, and screening gates are colored in blue, yellow, orange, and violet, respectively. The current flow is depicted by the dashed line. We aim at equalizing the pinch-off voltages of the plunger gates Pi. (b) Schematics of the strategy followed illustrated with only two gates for clarity. Note that here, in contrast to the illustration in Figure 2a, the pinch-off voltage Vthres is detected through lowering the gate voltage until I = Ithres. (c) Evolution of the pinch-off characteristics in device A after two iterations of the tuning procedure. The target voltage Vtarget = 1.05 V is marked by a red dashed line. After two iterations the spread of the pinch-off voltage ΔVthres is reduced from 153 mV to 20 mV. (d) Evolution of Vthres for each gate while Vstress is increased during the tuning procedure. The red dashed line indicates the target pinch-off voltage Vtarget = 1.05 V. The stressing on each gate is stopped when its pinch-off voltage becomes larger than Vtarget. The coloring of the data points encodes the time evolution of the stress and pinch-off voltages of the gates during each iteration.

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  • References

    This article references 56 other publications.

    1. 1
      Zwanenburg, F. A.; Dzurak, A. S.; Morello, A.; Simmons, M. Y.; Hollenberg, L. C. L.; Klimeck, G.; Rogge, S.; Coppersmith, S. N.; Eriksson, M. A. Silicon quantum electronics. Rev. Mod. Phys. 2013, 85, 961,  DOI: 10.1103/RevModPhys.85.961
      1
      Silicon quantum electronics
      Zwanenburg, Floris A.; Dzurak, Andrew S.; Morello, Andrea; Simmons, Michelle Y.; Hollenberg, Lloyd C. L.; Klimeck, Gerhard; Rogge, Sven; Coppersmith, Susan N.; Eriksson, Mark A.
      Reviews of Modern Physics (2013), 85 (3), 961-1019CODEN: RMPHAT; ISSN:0034-6861. (American Physical Society)
      This review describes recent groundbreaking results in Si, Si/SiGe, and dopant-based quantum dots, and it highlights the remarkable advances in Si-based quantum physics that have occurred in the past few years. This progress has been possible thanks to materials development of Si quantum devices, and the phys. understanding of quantum effects in silicon. Recent crit. steps include the isolation of single electrons, the observation of spin blockade, and single-shot readout of individual electron spins in both dopants and gated quantum dots in Si. Each of these results has come with physics that was not anticipated from previous work in other material systems. These advances underline the significant progress toward the realization of spin quantum bits in a material with a long spin coherence time, crucial for quantum computation and spintronics.
    2. 2
      Vandersypen, L. M. K.; Bluhm, H.; Clarke, J. S.; Dzurak, A. S.; Ishihara, R.; Morello, A.; Reilly, D. J.; Schreiber, L. R.; Veldhorst, M. Interfacing spin qubits in quantum dots and donors - hot, dense, and coherent. npj Quantum Inf 2017, 3, 34,  DOI: 10.1038/s41534-017-0038-y
      There is no corresponding record for this reference.
    3. 3
      Scappucci, G.; Kloeffel, C.; Zwanenburg, F. A.; Loss, D.; Myronov, M.; Zhang, J.-J.; De Franceschi, S.; Katsaros, G.; Veldhorst, M. The germanium quantum information route. Nature Reviews Materials 2021, 6, 926,  DOI: 10.1038/s41578-020-00262-z
      3
      The germanium quantum information route
      Scappucci, Giordano; Kloeffel, Christoph; Zwanenburg, Floris A.; Loss, Daniel; Myronov, Maksym; Zhang, Jian-Jun; De Franceschi, Silvano; Katsaros, Georgios; Veldhorst, Menno
      Nature Reviews Materials (2021), 6 (10), 926-943CODEN: NRMADL; ISSN:2058-8437. (Nature Portfolio)
      A review. In the effort to develop disruptive quantum technologies, germanium is emerging as a versatile material to realize devices capable of encoding, processing and transmitting quantum information. These devices leverage the special properties of holes in germanium, such as their inherently strong spin-orbit coupling and their ability to host superconducting pairing correlations. In this Review, we start by introducing the physics of holes in low-dimensional germanium structures, providing key insights from a theor. perspective. We then examine the materials-science progress underpinning germanium-based planar heterostructures and nanowires. We go on to review the most significant exptl. results demonstrating key building blocks for quantum technol., such as an elec. driven universal quantum gate set with spin qubits in quantum dots and superconductor-semiconductor devices for hybrid quantum systems. We conclude by identifying the most promising avenues towards scalable quantum information processing in germanium-based systems.
    4. 4
      Scappucci, G.; Taylor, P. J.; Williams, J. R.; Ginley, T.; Law, S. Crystalline materials for quantum computing: Semiconductor heterostructures and topological insulators exemplars. MRS Bull. 2021, 46, 596,  DOI: 10.1557/s43577-021-00147-8
      4
      Crystalline materials for quantum computing and Semiconductor heterostructures and topological insulators exemplars
      Scappucci, G.; Taylor, P. J.; Williams, J. R.; Ginley, T.; Law, S.
      MRS Bulletin (2021), 46 (7), 596-606CODEN: MRSBEA; ISSN:1938-1425. (Springer International Publishing AG)
      Abstr.: High-purity cryst. solid-state materials play an essential role in various technologies for quantum information processing, from qubits based on spins to topol. states. New and improved cryst. materials emerge each year and continue to drive new results in exptl. quantum science. This article summarizes the opportunities for a selected class of cryst. materials for qubit technologies based on spins and topol. states and the challenges assocd. with their fabrication. We start by describing semiconductor heterostructures for spin qubits in gate-defined quantum dots and benchmark GaAs, Si, and Ge, the three platforms that demonstrated two-qubit logic. We then examine novel topol. nontrivial materials and structures that might be incorporated into superconducting devices to create topol. qubits. We review topol. insulator thin films and move onto topol. cryst. materials, such as PbSnTe, and its integration with Josephson junctions. We discuss advances in novel and specialized fabrication and characterization techniques to enable these. We conclude by identifying the most promising directions where advances in these material systems will enable progress in qubit technol.
    5. 5
      Itoh, K. M.; Watanabe, H. Isotope engineering of silicon and diamond for quantum computing and sensing applications. MRS Commun. 2014, 4, 143– 157,  DOI: 10.1557/mrc.2014.32
      5
      Isotope engineering of silicon and diamond for quantum computing and sensing applications
      Itoh, Kohei M.; Watanabe, Hideyuki
      MRS Communications (2014), 4 (4), 143-157CODEN: MCROF8; ISSN:2159-6867. (Cambridge University Press)
      Some of the stable isotopes of silicon and carbon have zero nuclear spin, whereas many of the other elements that constitute semiconductors consist entirely of stable isotopes that have nuclear spins. Silicon and diamond crystals composed of nuclear-spin-free stable isotopes (28Si, 30Si, or 12C) are considered to be ideal host matrixes to place spin quantum bits (qubits) for quantum-computing and -sensing applications, because their coherent properties are not disrupted thanks to the absence of host nuclear spins. The present paper describes the state-of-the-art and future perspective of silicon and diamond isotope engineering for development of quantum information-processing devices.
    6. 6
      Veldhorst, M.; Hwang, J. C. C.; Yang, C. H.; Leenstra, A. W.; de Ronde, B.; Dehollain, J. P.; Muhonen, J. T.; Hudson, F. E.; Itoh, K. M.; Morello, A.; Dzurak, A. S. An addressable quantum dot qubit with fault-tolerant control-fidelity. Nat. Nanotechnol. 2014, 9, 981,  DOI: 10.1038/nnano.2014.216
      6
      An addressable quantum dot qubit with fault-tolerant control-fidelity
      Veldhorst, M.; Hwang, J. C. C.; Yang, C. H.; Leenstra, A. W.; de Ronde, B.; Dehollain, J. P.; Muhonen, J. T.; Hudson, F. E.; Itoh, K. M.; Morello, A.; Dzurak, A. S.
      Nature Nanotechnology (2014), 9 (12), 981-985CODEN: NNAABX; ISSN:1748-3387. (Nature Publishing Group)
      Exciting progress towards spin-based quantum computing has recently been made with qubits realized using N-vacancy centers in diamond and P atoms in Si. For example, long coherence times were made possible by the presence of spin-free isotopes of C and Si. However, despite promising single-atom nanotechnologies, there remain substantial challenges in coupling such qubits and addressing them individually. Conversely, lithog. defined quantum dots have an exchange coupling that can be precisely engineered, but strong coupling to noise has severely limited their dephasing times and control fidelities. Here, we combine the best aspects of both spin qubit schemes and demonstrate a gate-addressable quantum dot qubit in isotopically engineered Si with a control fidelity of 99.6%, obtained via Clifford-based randomized benchmarking and consistent with that required for fault-tolerant quantum computing. This qubit has dephasing time T2* = 120 μs and coherence time T2 = 28 ms, both orders of magnitude larger than in other types of semiconductor qubit. By gate-voltage-tuning the electron g*-factor we can Stark shift the ESR frequency by more than 3,000 times the 2.4 kHz ESR linewidth, providing a direct route to large-scale arrays of addressable high-fidelity qubits that are compatible with existing manufg. technologies.
    7. 7
      Stano, P.; Loss, D. Review of performance metrics of spin qubits in gated semiconducting nanostructures. Nature Review Physics 2022, 4, 672,  DOI: 10.1038/s42254-022-00484-w
      There is no corresponding record for this reference.
    8. 8
      Dehollain, J. P.; Muhonen, J. T.; Blume-Kohout, R.; Rudinger, K. M.; King Gamble, J.; Nielsen, E.; Laucht, A.; Simmons, S.; Kalra, R.; Dzurak, A. S.; Morello, A. Optimization of a solid-state electron spin qubit using gate set tomography. New J. Phys. 2016, 18, 103018,  DOI: 10.1088/1367-2630/18/10/103018
      8
      Optimization of a solid-state electron spin qubit using gate set tomography
      Dehollain, Juan P.; Muhonen, Juha T.; Blume-Kohout, Robin; Rudinger, Kenneth M.; Gamble, John King; Nielsen, Erik; Laucht, Arne; Simmons, Stephanie; Kalra, Rachpon; Dzurak, Andrew S.; Morello, Andrea
      New Journal of Physics (2016), 18 (Oct.), 103018/1-103018/9CODEN: NJOPFM; ISSN:1367-2630. (IOP Publishing Ltd.)
      State of the art qubit systems are reaching the gate fidelities required for scalable quantum computation architectures. Further improvements in the fidelity of quantum gates demands characterization and benchmarking protocols that are efficient, reliable and extremely accurate. Ideally, a benchmarking protocol should also provide information on how to rectify residual errors. Gate set tomog. (GST) is one such protocol designed to give detailed characterization of as-built qubits. We implemented GST on a high-fidelity electron-spin qubit confined by a single 31P atom in 28Si. The results reveal systematic errors that a randomized benchmarking anal. could measure but not identify, whereas GST indicated the need for improved calibration of the length of the control pulses. After introducing this modification, we measured a new benchmark av. gate fidelity of 99.942(8)%, an improvement on the previous value of 99.90(2)%. Furthermore, GST revealed high levels of non-Markovian noise in the system, which will need to be understood and addressed when the qubit is used within a fault-tolerant quantum computation scheme.
    9. 9
      Yoneda, J.; Takeda, K.; Otsuka, T.; Nakajima, T.; Delbecq, M. R.; Allison, G.; Honda, T.; Kodera, T.; Oda, S.; Hoshi, Y.; Noritaka, U.; Itoh, K. M.; Tarucha, S. A quantum-dot spin qubit with coherence limited by charge noise and fidelity higher than 99.9%. Nat. Nanotechnol. 2018, 13, 102,  DOI: 10.1038/s41565-017-0014-x
      9
      A quantum-dot spin qubit with coherence limited by charge noise and fidelity higher than 99.9%
      Yoneda, Jun; Takeda, Kenta; Otsuka, Tomohiro; Nakajima, Takashi; Delbecq, Matthieu R.; Allison, Giles; Honda, Takumu; Kodera, Tetsuo; Oda, Shunri; Hoshi, Yusuke; Usami, Noritaka; Itoh, Kohei M.; Tarucha, Seigo
      Nature Nanotechnology (2018), 13 (2), 102-106CODEN: NNAABX; ISSN:1748-3387. (Nature Research)
      The isolation of qubits from noise sources, such as surrounding nuclear spins and spin-elec. susceptibility, has enabled extensions of quantum coherence times in recent pivotal advances towards the concrete implementation of spin-based quantum computation. In fact, the possibility of achieving enhanced quantum coherence has been substantially doubted for nanostructures due to the characteristic high degree of background charge fluctuations. Still, a sizeable spin-elec. coupling will be needed in realistic multiple-qubit systems to address single-spin and spin-spin manipulations. Here, we realize a single-electron spin qubit with an isotopically enriched phase coherence time (20 μs) and fast elec. control speed (up to 30 MHz) mediated by extrinsic spin-elec. coupling. Using rapid spin rotations, we reveal that the free-evolution dephasing is caused by charge noise - rather than conventional magnetic noise - as highlighted by a 1/f spectrum extended over seven decades of frequency. The qubit exhibits superior performance with single-qubit gate fidelities exceeding 99.9% on av., offering a promising route to large-scale spin-qubit systems with fault-tolerant controllability. Quantum control on an isotopically enriched Si spin qubit is demonstrated with ultrahigh gate fidelities and long coherence times - even in the presence of sizeable charge noise.
    10. 10
      Lawrie, W. I. L.; Russ, M.; van Riggelen, F.; Hendrickx, N. W.; de Snoo, S. L.; Sammak, A.; Vandersypen, L. M. K.; Scappucci, G.; Veldhorst, M. Simultaneous driving of semiconductor spin qubits at the fault-tolerant threshold. arXiv, 2109.07837 (2021).
      There is no corresponding record for this reference.
    11. 11
      Mądzik, M.; Asaad, S.; Youssry, A.; Joecker, B.; Rudinger, K. M.; Nielsen, E.; Young, K. C.; Proctor, T. J.; Baczewski, A. D.; Laucht, A.; Schmitt, V.; Hudson, F. E.; Itoh, K. M.; Jakob, A. M.; Johnson, B. C.; Jamieson, D. N.; Dzurak, A. S.; Ferrie, C.; Blume-Kohout, R.; Morello, A. Precision tomography of a three-qubit donor quantum processor in silicon. Nature 2022, 601, 348,  DOI: 10.1038/s41586-021-04292-7
      11
      Precision tomography of a three-qubit donor quantum processor in silicon
      Madzik, Mateusz T.; Asaad, Serwan; Youssry, Akram; Joecker, Benjamin; Rudinger, Kenneth M.; Nielsen, Erik; Young, Kevin C.; Proctor, Timothy J.; Baczewski, Andrew D.; Laucht, Arne; Schmitt, Vivien; Hudson, Fay E.; Itoh, Kohei M.; Jakob, Alexander M.; Johnson, Brett C.; Jamieson, David N.; Dzurak, Andrew S.; Ferrie, Christopher; Blume-Kohout, Robin; Morello, Andrea
      Nature (London, United Kingdom) (2022), 601 (7893), 348-353CODEN: NATUAS; ISSN:1476-4687. (Nature Portfolio)
      Abstr.: Nuclear spins were among the first phys. platforms to be considered for quantum information processing1,2, because of their exceptional quantum coherence3 and at.-scale footprint. However, their full potential for quantum computing has not yet been realized, owing to the lack of methods with which to link nuclear qubits within a scalable device combined with multi-qubit operations with sufficient fidelity to sustain fault-tolerant quantum computation. Here we demonstrate universal quantum logic operations using a pair of ion-implanted 31P donor nuclei in a silicon nanoelectronic device. A nuclear two-qubit controlled-Z gate is obtained by imparting a geometric phase to a shared electron spin4, and used to prep. entangled Bell states with fidelities up to 94.2(2.7)%. The quantum operations are precisely characterized using gate set tomog. (GST)5, yielding one-qubit av. gate fidelities up to 99.95(2)%, two-qubit av. gate fidelity of 99.37(11)% and two-qubit prepn./measurement fidelities of 98.95(4)%. These three metrics indicate that nuclear spins in silicon are approaching the performance demanded in fault-tolerant quantum processors6. We then demonstrate entanglement between the two nuclei and the shared electron by producing a Greenberger-Horne-Zeilinger three-qubit state with 92.5(1.0)% fidelity. Because electron spin qubits in semiconductors can be further coupled to other electrons7-9 or phys. shuttled across different locations10,11, these results establish a viable route for scalable quantum information processing using donor nuclear and electron spins.
    12. 12
      Noiri, A.; Takeda, K.; Nakajima, T.; Kobayashi, T.; Sammak, A.; Scappucci, G.; Tarucha, S. Fast universal quantum gate above the fault-tolerance threshold in silicon. Nature 2022, 601, 338,  DOI: 10.1038/s41586-021-04182-y
      12
      Fast universal quantum gate above the fault-tolerance threshold in silicon
      Noiri, Akito; Takeda, Kenta; Nakajima, Takashi; Kobayashi, Takashi; Sammak, Amir; Scappucci, Giordano; Tarucha, Seigo
      Nature (London, United Kingdom) (2022), 601 (7893), 338-342CODEN: NATUAS; ISSN:1476-4687. (Nature Portfolio)
      Fault-tolerant quantum computers that can solve hard problems rely on quantum error correction1. One of the most promising error correction codes is the surface code2, which requires universal gate fidelities exceeding an error correction threshold of 99 per cent3. Among the many qubit platforms, only superconducting circuits4, trapped ions5 and nitrogen-vacancy centers in diamond6 have delivered this requirement. Electron spin qubits in silicon7-15 are particularly promising for a large-scale quantum computer owing to their nanofabrication capability, but the two-qubit gate fidelity has been limited to 98 per cent owing to the slow operation16. Here we demonstrate a two-qubit gate fidelity of 99.5 per cent, along with single-qubit gate fidelities of 99.8 per cent, in silicon spin qubits by fast elec. control using a micromagnet-induced gradient field and a tunable two-qubit coupling. We identify the qubit rotation speed and coupling strength where we robustly achieve high-fidelity gates. We realize Deutsch-Jozsa and Grover search algorithms with high success rates using our universal gate set. Our results demonstrate universal gate fidelity beyond the fault-tolerance threshold and may enable scalable silicon quantum computers.
    13. 13
      Xue, X.; Russ, M.; Samkharadze, N.; Undseth, B.; Sammak, A.; Scappucci, G.; Vandersypen, L. M. K. Quantum logic with spin qubits crossing the surface code threshold. Nature 2022, 601, 343,  DOI: 10.1038/s41586-021-04273-w
      13
      Quantum logic with spin qubits crossing surface code threshold
      Xue, Xiao; Russ, Maximilian; Samkharadze, Nodar; Undseth, Brennan; Sammak, Amir; Scappucci, Giordano; Vandersypen, Lieven M. K.
      Nature (London, United Kingdom) (2022), 601 (7893), 343-347CODEN: NATUAS; ISSN:1476-4687. (Nature Portfolio)
      High-fidelity control of quantum bits is paramount for the reliable execution of quantum algorithms and for achieving fault tolerance-the ability to correct errors faster than they occur1. The central requirement for fault tolerance is expressed in terms of an error threshold. Whereas the actual threshold depends on many details, a common target is the approx. 1% error threshold of the well-known surface code2,3. Reaching two-qubit gate fidelities above 99% has been a long-standing major goal for semiconductor spin qubits. These qubits are promising for scaling, as they can leverage advanced semiconductor technol.4. Here we report a spin-based quantum processor in silicon with single-qubit and two-qubit gate fidelities, all of which are above 99.5%, extd. from gate-set tomog. The av. single-qubit gate fidelities remain above 99% when including crosstalk and idling errors on the neighboring qubit. Using this high-fidelity gate set, we execute the demanding task of calcg. mol. ground-state energies using a variational quantum eigensolver algorithm5. Having surpassed the 99% barrier for the two-qubit gate fidelity, semiconductor qubits are well positioned on the path to fault tolerance and to possible applications in the era of noisy intermediate-scale quantum devices.
    14. 14
      Hendrickx, N. W.; Lawrie, W. I. L.; Russ, M.; van Riggelen, F.; de Snoo, S. L.; Schouten, R. N.; Sammak, A.; Scappucci, G.; Veldhorst, M. A four-qubit germanium quantum processor. Nature 2021, 591, 580,  DOI: 10.1038/s41586-021-03332-6
      14
      A four-qubit germanium quantum processor
      Hendrickx, Nico W.; Lawrie, William I. L.; Russ, Maximilian; van Riggelen, Floor; de Snoo, Sander L.; Schouten, Raymond N.; Sammak, Amir; Scappucci, Giordano; Veldhorst, Menno
      Nature (London, United Kingdom) (2021), 591 (7851), 580-585CODEN: NATUAS; ISSN:0028-0836. (Nature Research)
      The prospect of building quantum circuits1,2 using advanced semiconductor manufg. makes quantum dots an attractive platform for quantum information processing3,4. Extensive studies of various materials have led to demonstrations of two-qubit logic in gallium arsenide5, silicon6-12 and germanium13. However, interconnecting larger nos. of qubits in semiconductor devices has remained a challenge. Here we demonstrate a four-qubit quantum processor based on hole spins in germanium quantum dots. Furthermore, we define the quantum dots in a two-by-two array and obtain controllable coupling along both directions. Qubit logic is implemented all-elec. and the exchange interaction can be pulsed to freely program one-qubit, two-qubit, three-qubit and four-qubit operations, resulting in a compact and highly connected circuit. We execute a quantum logic circuit that generates a four-qubit Greenberger-Horne-Zeilinger state and we obtain coherent evolution by incorporating dynamical decoupling. These results are a step towards quantum error correction and quantum simulation using quantum dots.
    15. 15
      Philips, S. G. J.; Mądzik, M. T.; Amitonov, S. V.; de Snoo, S. L.; Russ, M.; Kalhor, N.; Volk, C.; Lawrie, W. I. L.; Brousse, D.; Tryputen, L.; Paquelet Wuetz, B.; Sammak, A.; Veldhorst, M.; Scappucci, G.; Vandersypen, L. M. K. Universal control of a six-qubit quantum processor in silicon. Nature 2022, 609, 919– 924,  DOI: 10.1038/s41586-022-05117-x
      15
      Universal control of a six-qubit quantum processor in silicon
      Philips, Stephan G. J.; Madzik, Mateusz T.; Amitonov, Sergey V.; de Snoo, Sander L.; Russ, Maximilian; Kalhor, Nima; Volk, Christian; Lawrie, William I. L.; Brousse, Delphine; Tryputen, Larysa; Wuetz, Brian Paquelet; Sammak, Amir; Veldhorst, Menno; Scappucci, Giordano; Vandersypen, Lieven M. K.
      Nature (London, United Kingdom) (2022), 609 (7929), 919-924CODEN: NATUAS; ISSN:1476-4687. (Nature Portfolio)
      Future quantum computers capable of solving relevant problems will require a large no. of qubits that can be operated reliably1. However, the requirements of having a large qubit count and operating with high fidelity are typically conflicting. Spins in semiconductor quantum dots show long-term promise2,3 but demonstrations so far use between one and four qubits and typically optimize the fidelity of either single- or two-qubit operations, or initialization and readout4-11. Here, we increase the no. of qubits and simultaneously achieve respectable fidelities for universal operation, state prepn. and measurement. We design, fabricate and operate a six-qubit processor with a focus on careful Hamiltonian engineering, on a high level of abstraction to program the quantum circuits, and on efficient background calibration, all of which are essential to achieve high fidelities on this extended system. State prepn. combines initialization by measurement and real-time feedback with quantum-non-demolition measurements. These advances will enable testing of increasingly meaningful quantum protocols and constitute a major stepping stone towards large-scale quantum computers.
    16. 16
      Petit, L.; Eenink, H. G. J.; Russ, M.; Lawrie, W. I. L.; Hendrickx, N. W.; Phillips, S. G. J.; Clarke, J. S.; Vandersypen, L. M. K.; Veldhorst, M. Universal quantum logic in hot silicon qubits. Nature 2020, 580, 355,  DOI: 10.1038/s41586-020-2170-7
      16
      Universal quantum logic in hot silicon qubits
      Petit, L.; Eenink, H. G. J.; Russ, M.; Lawrie, W. I. L.; Hendrickx, N. W.; Philips, S. G. J.; Clarke, J. S.; Vandersypen, L. M. K.; Veldhorst, M.
      Nature (London, United Kingdom) (2020), 580 (7803), 355-359CODEN: NATUAS; ISSN:0028-0836. (Nature Research)
      Quantum computation requires many qubits that can be coherently controlled and coupled to each other. Qubits that are defined using lithog. techniques have been suggested to enable the development of scalable quantum systems because they can be implemented using semiconductor fabrication technol. However, leading solid-state approaches function only at temps. below 100 mK, where cooling power is extremely limited, and this severely affects the prospects of practical quantum computation. Recent studies of electron spins in silicon have made progress towards a platform that can be operated at higher temps. by demonstrating long spin lifetimes, gate-based spin readout and coherent single-spin control. However, a high-temp. two-qubit logic gate has not yet been demonstrated. Here, the authors show that silicon quantum dots can have sufficient thermal robustness to enable the execution of a universal gate set at temps. greater than one kelvin. They obtain single-qubit control via ESR and readout using Pauli spin blockade. In addn., they show individual coherent control of two qubits and measure single-qubit fidelities of up to 99.3%. They demonstrate the tunability of the exchange interaction between the two spins from 0.5 to 18 MHz and use it to execute coherent two-qubit controlled rotations. The demonstration of 'hot' and universal quantum logic in a semiconductor platform paves the way for quantum integrated circuits that host both the quantum hardware and its control circuitry on the same chip, providing a scalable approach towards practical quantum information processing.
    17. 17
      Yang, C. H.; Leon, R. C. C.; Hwang, J. C. C.; Saraiva, A.; Tanttu, T.; Huang, W.; Camirand Lemyre, J.; Chan, K. W.; Tan, K. Y.; Hudson, F. E.; Itoh, K. M.; Morello, A.; Pioro-Ladrière, M.; Laucht, A.; Dzurak, A. S. Operation of a silicon quantum processor unit cell above one kelvin. Nature 2020, 580, 350,  DOI: 10.1038/s41586-020-2171-6
      17
      Operation of a silicon quantum processor unit cell above one kelvin
      Yang, C. H.; Leon, R. C. C.; Hwang, J. C. C.; Saraiva, A.; Tanttu, T.; Huang, W.; Camirand Lemyre, J.; Chan, K. W.; Tan, K. Y.; Hudson, F. E.; Itoh, K. M.; Morello, A.; Pioro-Ladriere, M.; Laucht, A.; Dzurak, A. S.
      Nature (London, United Kingdom) (2020), 580 (7803), 350-354CODEN: NATUAS; ISSN:0028-0836. (Nature Research)
      Abstr.: Quantum computers are expected to outperform conventional computers in several important applications, from mol. simulation to search algorithms, once they can be scaled up to large nos.-typically millions-of quantum bits (qubits)1-3. For most solid-state qubit technologies-for example, those using superconducting circuits or semiconductor spins-scaling poses a considerable challenge because every addnl. qubit increases the heat generated, whereas the cooling power of diln. refrigerators is severely limited at their operating temp. (less than 100 mK)4-6. Here we demonstrate the operation of a scalable silicon quantum processor unit cell comprising two qubits confined to quantum dots at about 1.5 K. We achieve this by isolating the quantum dots from the electron reservoir, and then initializing and reading the qubits solely via tunnelling of electrons between the two quantum dots7-9. We coherently control the qubits using elec. driven spin resonance10,11 in isotopically enriched silicon1228Si, attaining single-qubit gate fidelities of 98.6 per cent and a coherence time of 2μs during 'hot' operation, comparable to those of spin qubits in natural silicon at millikelvin temps.13-16. Furthermore, we show that the unit cell can be operated at magnetic fields as low as 0.1 T, corresponding to a qubit control frequency of 3.5 GHz, where the qubit energy is well below the thermal energy. The unit cell constitutes the core building block of a full-scale silicon quantum computer and satisfies layout constraints required by error-correction architectures8,17. Our work indicates that a spin-based quantum computer could be operated at increased temps. in a simple pumped 4He system (which provides cooling power orders of magnitude higher than that of diln. refrigerators), thus potentially enabling the integration of classical control electronics with the qubit array18,19.
    18. 18
      Camenzind, L. C.; Geyer, S.; Fuhrer, A.; Warburton, R. J.; Zumbühl, D. M.; Kuhlmann, A. V. A hole spin qubit in a fin field-effect transistor above 4 Kelvin. Nature Electronics 2022, 5, 178,  DOI: 10.1038/s41928-022-00722-0
      There is no corresponding record for this reference.
    19. 19
      Ansaloni, F.; Chatterjee, A.; Bohuslavskyi, H.; Bertrand, B.; Hutin, L.; Vinet, M.; Kuemmeth, F. Single-electron operations in a foundry-fabricated array of quantum dots. Nat. Commun. 2020, 11, 6399,  DOI: 10.1038/s41467-020-20280-3
      19
      Single-electron operations in a foundry-fabricated array of quantum dots
      Ansaloni, Fabio; Chatterjee, Anasua; Bohuslavskyi, Heorhii; Bertrand, Benoit; Hutin, Louis; Vinet, Maud; Kuemmeth, Ferdinand
      Nature Communications (2020), 11 (1), 6399CODEN: NCAOBW; ISSN:2041-1723. (Nature Research)
      Silicon quantum dots are attractive for the implementation of large spin-based quantum processors in part due to prospects of industrial foundry fabrication. However, the large effective mass assocd. with electrons in silicon traditionally limits single-electron operations to devices fabricated in customized academic clean rooms. Here, we demonstrate single-electron occupations in all four quantum dots of a 2 x 2 split-gate silicon device fabricated entirely by 300-mm-wafer foundry processes. By applying gate-voltage pulses while performing high-frequency reflectometry off one gate electrode, we perform single-electron operations within the array that demonstrate single-shot detection of electron tunneling and an overall adjustability of tunneling times by a global top gate electrode. Lastly, we use the two-dimensional aspect of the quantum dot array to exchange two electrons by spatial permutation, which may find applications in permutation-based quantum algorithms.
    20. 20
      Zwerver, A.-M. J.; Krähenmann, T.; Watson, T. F.; Lampert, L.; George, H. C.; Pillarisetty, R.; Bojarski, S. A.; Amin, P.; Amitonov, S. V.; Boter, J. M.; Caudillo, R.; Corras-Serrano, D.; Dehollain, J. P.; Droulers, G.; Henry, E. M.; Kotlyar, R.; Lodari, M.; Lüthi, F.; Michalak, D. J.; Mueller, B. K.; Neyens, S.; Roberts, J.; Samkharadze, N.; Zheng, G.; Zietz, O. K.; Scappucci, G.; Veldhorst, M.; Vandersypen, L. M. K.; Clarke, J. S. Qubits made by advanced semiconductor manufacturing. Nature Electronics 2022, 5, 184,  DOI: 10.1038/s41928-022-00727-9
      There is no corresponding record for this reference.
    21. 21
      Bavdaz, P. L.; Eenink, H. G. J.; van Staveren, J.; Lodari, M.; Almudever, C. G.; Clarke, J. S.; Sebastiano, F.; Veldhorst, M.; Scappucci, G. A quantum dot crossbar with sublinear scaling of interconnects at cryogenic temperature. npj Quantum Information 2022, 8, 86,  DOI: 10.1038/s41534-022-00597-1
      There is no corresponding record for this reference.
    22. 22
      Hill, C. D.; Peretz, E.; Hile, S. J.; House, M. G.; Fuechsle, M.; Rogge, S.; Simmons, M. Y.; Hollenberg, L. C. L. A surface code quantum computer in silicon. Science Advances 2015, 1, e1500707  DOI: 10.1126/sciadv.1500707
      22
      A surface code quantum computer in silicon
      Hill, Charles D.; Peretz, Eldad; Hile, Samuel J.; House, Matthew G.; Fuechsle, Martin; Rogge, Sven; Simmons, Michelle Y.; Hollenberg, Lloyd C. L.
      Science Advances (2015), 1 (9), e1500707/1-e1500707/11CODEN: SACDAF; ISSN:2375-2548. (American Association for the Advancement of Science)
      The exceptionally long quantum coherence times of phosphorus donor nuclear spin qubits in silicon, coupled with the proven scalability of silicon-based nano-electronics, make them attractive candidates for large-scale quantum computing. However, the high threshold of topol. quantum error correction can only be captured in a two-dimensional array of qubits operating synchronously and in parallel-posing formidable fabrication and control challenges. We present an architecture that addresses these problems through a novel shared-control paradigm that is particularly suited to the natural uniformity of the phosphorus donor nuclear spin qubit states and electronic confinement. The architecture comprises a two-dimensional lattice of donor qubits sandwiched between two vertically sepd. control layers forming a mutually perpendicular crisscross gate array. Shared-control lines facilitate loading/unloading of single electrons to specific donors, thereby activating multiple qubits in parallel across the array on which the required operations for surface code quantum error correction are carried out by global spin control. The complexities of independent qubit control, wave function engineering, and ad hoc quantum interconnects are explicitly avoided. With many of the basic elements of fabrication and control based on demonstrated techniques and with simulated quantum operation below the surface code error threshold, the architecture represents a new pathway for large-scale quantum information processing in silicon and potentially in other qubit systems where uniformity can be exploited.
    23. 23
      Veldhorst, M.; Eenink, H. G. J.; Yang, C. H.; Dzurak, A. S. Silicon CMOS architecture for a spin-based quantum computer. Nat. Commun. 2017, 8, 1766,  DOI: 10.1038/s41467-017-01905-6
      23
      Silicon CMOS architecture for a spin-based quantum computer
      Veldhorst M; Eenink H G J; Veldhorst M; Eenink H G J; Yang C H; Dzurak A S
      Nature communications (2017), 8 (1), 1766 ISSN:.
      Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.
    24. 24
      Li, R.; Petit, L.; Franke, D. P.; Dehollain, J. P.; Helsen, J.; Steudtner, M.; Thomas, N. K.; Yoscovits, Z. R.; Singh, K. J.; Wehner, S.; Vandersypen, L. M. K.; Clarke, J. S.; Veldhorst, M. A crossbar network for silicon quantum dot qubits. Science Advances 2018, 4, eaar3960  DOI: 10.1126/sciadv.aar3960
      There is no corresponding record for this reference.
    25. 25
      Thorbeck, T.; Zimmerman, N. M. Formation of strain-induced quantum dots in gated semiconductor nanostructures. AIP Advances 2015, 5, 087107,  DOI: 10.1063/1.4928320
      25
      Formation of strain-induced quantum dots in gated semiconductor nanostructures
      Thorbeck, Ted; Zimmerman, Neil M.
      AIP Advances (2015), 5 (8), 087107/1-087107/10CODEN: AAIDBI; ISSN:2158-3226. (American Institute of Physics)
      A long-standing mystery in the field of semiconductor quantum dots (QDs) is: Why are there so many unintentional dots (also known as disorder dots) which are neither expected nor controllable. It is typically assumed that these unintentional dots are due to charged defects, however the frequency and predictability of the location of the unintentional QDs suggests there might be addnl. mechanisms causing the unintentional QDs besides charged defects. We show that the typical strains in a semiconductor nanostructure from metal gates are large enough to create strain-induced quantum dots. We simulate a commonly used QD device architecture, metal gates on bulk silicon, and show the formation of strain-induced QDs. The strain-induced QD can be eliminated by replacing the metal gates with poly-silicon gates. Thus strain can be as important as electrostatics to QD device operation operation. (c) 2015 American Institute of Physics.
    26. 26
      Stein, R. M.; Barcikowski, Z. S.; Pookpanratana, S. J.; Pomeroy, J. M.; Stewart, M. D., Jr. Alternatives to aluminum gates for silicon quantum devices: Defects and strain. J. Appl. Phys. 2021, 130, 115102,  DOI: 10.1063/5.0061369
      26
      Alternatives to aluminum gates for silicon quantum devices: Defects and strain
      Stein, Ryan M.; Barcikowski, Z. S.; Pookpanratana, S. J.; Pomeroy, J. M.; Stewart, M. D.
      Journal of Applied Physics (Melville, NY, United States) (2021), 130 (11), 115102CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)
      Gate-defined quantum dots benefit from the use of small grain size metals for gate materials because they aid in shrinking the device dimensions. However, it is not clear what differences arise with respect to process-induced defect densities and inhomogeneous strain. Here, we present measurements of fixed charge, Qf; interface trap d., Dit; the intrinsic film stress, σ; and the coeff. of thermal expansion, α, as a function of forming gas anneal temp. for Al, Ti/Pd, and Ti/Pt gates. We show that Dit is minimized at an anneal temp. of 350°C for all materials, but Ti/Pd and Ti/Pt have higher Qf and Dit compared to Al. In addn., σ and α increase with anneal temp. for all three metals with α larger than the bulk value. These results indicate that there is a trade-off between minimizing defects and minimizing the impact of strain in quantum device fabrication. (c) 2021 American Institute of Physics.
    27. 27
      Lawrie, W. I. L.; Eenink, H. G. J.; Hendrickx, N. W.; Boter, J. M.; Petit, L.; Amitonov, S. V.; Lodari, M.; Paquelet Wuetz, B.; Volk, C.; Philips, S. G. J.; Droulers, G.; Kalhor, N.; van Riggelen, F.; Brousse, D.; Sammak, A.; Vandersypen, L. M. K.; Scappucci, G.; Veldhorst, M. Quantum dot arrays in silicon and germanium. Appl. Phys. Lett. 2020, 116, 080501,  DOI: 10.1063/5.0002013
      27
      Quantum dot arrays in silicon and germanium
      Lawrie, W. I. L.; Eenink, H. G. J.; Hendrickx, N. W.; Boter, J. M.; Petit, L.; Amitonov, S. V.; Lodari, M.; Paquelet Wuetz, B.; Volk, C.; Philips, S. G. J.; Droulers, G.; Kalhor, N.; van Riggelen, F.; Brousse, D.; Sammak, A.; Vandersypen, L. M. K.; Scappucci, G.; Veldhorst, M.
      Applied Physics Letters (2020), 116 (8), 080501CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
      Electrons and holes confined in quantum dots define excellent building blocks for quantum emergence, simulation, and computation. Silicon and germanium are compatible with std. semiconductor manufg. and contain stable isotopes with zero nuclear spin, thereby serving as excellent hosts for spins with long quantum coherence. Here, we demonstrate quantum dot arrays in a silicon metal-oxide-semiconductor (SiMOS), strained silicon (Si/SiGe), and strained germanium (Ge/SiGe). We fabricate using a multi-layer technique to achieve tightly confined quantum dots and compare integration processes. While SiMOS can benefit from a larger temp. budget and Ge/SiGe can make an Ohmic contact to metals, the overlapping gate structure to define the quantum dots can be based on a nearly identical integration. We realize charge sensing in each platform, for the first time in Ge/SiGe, and demonstrate fully functional linear and two-dimensional arrays where all quantum dots can be depleted to the last charge state. In Si/SiGe, we tune a quintuple quantum dot using the N + 1 method to simultaneously reach the few electron regime for each quantum dot. We compare capacitive crosstalk and find it to be the smallest in SiMOS, relevant for the tuning of quantum dot arrays. We put these results into perspective for quantum technol. and identify industrial qubits, hybrid technol., automated tuning, and two-dimensional qubit arrays as four key trajectories that, when combined, enable fault-tolerant quantum computation. (c) 2020 American Institute of Physics.
    28. 28
      Borsoi, F.; Hendrickx, N. W.; John, V.; Motz, S.; van Riggelen, F.; Sammak, A.; de Snoo, S. L.; Scappucci, G.; Veldhorst, M. Shared control of a 16 semiconductor quantum dot crossbar array. arXiv, 2209.06609 (2022).
      There is no corresponding record for this reference.
    29. 29
      Zajac, D. M.; Hazard, T. M.; Mi, X.; Nielsen, E.; Petta, J. R. Scalable gate architecture for a one-dimensional array of semiconductor spin qubits. Physical Review Applied 2016, 6, 054013,  DOI: 10.1103/PhysRevApplied.6.054013
      29
      Scalable gate architecture for a one-dimensional array of semiconductor spin qubits
      Zajac, D. M.; Hazard, T. M.; Mi, X.; Nielsen, E.; Petta, J. R.
      Physical Review Applied (2016), 6 (5), 054013/1-054013/8CODEN: PRAHB2; ISSN:2331-7019. (American Physical Society)
      We demonstrate a 12-quantum-dot device fabricated on an undoped Si/SiGe heterostructure as a proof of concept for a scalable, linear gate architecture for semiconductor quantum dots. The device consists of nine quantum dots in a linear array and three single-quantum-dot charge sensors. We show reproducible single-quantum-dot charging and orbital energies, with std. deviations less than 20% relative to the mean across the nine-dot array. The single-quantum-dot charge sensors have a charge sensitivity of 8.2 × 10-4 e/ √HZ and allow for the investigation of real-time charge dynamics. As a demonstration of the versatility of this device, we use single-shot readout to measure the spin-relaxation time T1 170 ms at a magnetic field B =1 T. By reconfiguring the device, we form two capacitively coupled double quantum dots and ext. a mutual charging energy of 200 μeV, which indicates that 50-GHz two-qubit gate-operation speeds are feasible.
    30. 30
      Mills, A. R.; Zajac, D. M.; Gullans, M. J.; Schupp, F. J.; Hazard, T. M.; Petta, J. R. Shuttling a single charge across a one-dimensional array of silicon quantum dots. Nat. Commun. 2019, 10, 1063,  DOI: 10.1038/s41467-019-08970-z
      30
      Shuttling a single charge across a one-dimensional array of silicon quantum dots
      Mills A R; Zajac D M; Gullans M J; Schupp F J; Hazard T M; Petta J R
      Nature communications (2019), 10 (1), 1063 ISSN:.
      Significant advances have been made towards fault-tolerant operation of silicon spin qubits, with single qubit fidelities exceeding 99.9%, several demonstrations of two-qubit gates based on exchange coupling, and the achievement of coherent single spin-photon coupling. Coupling arbitrary pairs of spatially separated qubits in a quantum register poses a significant challenge as most qubit systems are constrained to two dimensions with nearest neighbor connectivity. For spins in silicon, new methods for quantum state transfer should be developed to achieve connectivity beyond nearest-neighbor exchange. Here we demonstrate shuttling of a single electron across a linear array of nine series-coupled silicon quantum dots in ~50 ns via a series of pairwise interdot charge transfers. By constructing more complex pulse sequences we perform parallel shuttling of two and three electrons at a time through the array. These experiments demonstrate a scalable approach to physically transporting single electrons across large silicon quantum dot arrays.
    31. 31
      Dodson, J. P.; Holman, N.; Thorgrimsson, B.; Neyens, S. F.; MacQuarrie, E. R.; McJunkin, T.; Foote, R. H.; Edge, L. F.; Coppersmith, S. N.; Eriksson, M. A. Fabrication process and failure analysis for robust quantum dots in silicon. Nanotechnology 2020, 31, 505001,  DOI: 10.1088/1361-6528/abb559
      31
      Fabrication process and failure analysis for robust quantum dots in silicon
      Dodson, J. P.; Holman, Nathan; Thorgrimsson, Brandur; Neyens, Samuel F.; MacQuarrie, E. R.; McJunkin, Thomas; Foote, Ryan H.; Edge, L. F.; Coppersmith, S. N.; Eriksson, M. A.
      Nanotechnology (2020), 31 (50), 505001CODEN: NNOTER; ISSN:1361-6528. (IOP Publishing Ltd.)
      We present an improved fabrication process for overlapping aluminum gate quantum dot devices on Si/SiGe heterostructures that incorporates low-temp. inter-gate oxidn., thermal annealing of gate oxide, on-chip electrostatic discharge (ESD) protection and an optimized interconnect process for thermal budget considerations. This process reduces gate-to-gate leakage, damage from ESD, dewetting of aluminum and formation of undesired alloys in device interconnects. Addnl., cross-sectional scanning transmission electron microscopy (STEM) images elucidate gate electrode morphol. in the active region as device geometry is varied. We show that overlapping aluminum gate layers homogeneously conform to the topol. beneath them, independent of gate geometry and identify crit. dimensions in the gate geometry where pattern transfer becomes non-ideal, causing device failure.
    32. 32
      Ha, W.; Ha, S. D.; Choi, M. D.; Tang, Y.; Schmitz, A. E.; Levendorf, M. P.; Lee, K.; Chappell, J. M.; Adams, T. S.; Hulbert, D. R.; Acuna, E.; Noah, R. S.; Matten, J. W.; Jura, M. P.; Wright, J. A.; Rakher, M. T.; Borselli, M. G. A flexible design platform for Si/SiGe exchange-only qubits with low disorder. Nano Lett. 2022, 22, 1443,  DOI: 10.1021/acs.nanolett.1c03026
      32
      A Flexible Design Platform for Si/SiGe Exchange-Only Qubits with Low Disorder
      Ha, Wonill; Ha, Sieu D.; Choi, Maxwell D.; Tang, Yan; Schmitz, Adele E.; Levendorf, Mark P.; Lee, Kangmu; Chappell, James M.; Adams, Tower S.; Hulbert, Daniel R.; Acuna, Edwin; Noah, Ramsey S.; Matten, Justine W.; Jura, Michael P.; Wright, Jeffrey A.; Rakher, Matthew T.; Borselli, Matthew G.
      Nano Letters (2022), 22 (3), 1443-1448CODEN: NALEFD; ISSN:1530-6984. (American Chemical Society)
      Spin-based silicon quantum dots are an attractive qubit technol. for quantum information processing with respect to coherence time, control, and engineering. Here we present an exchange-only Si qubit device platform that combines the throughput of CMOS-like wafer processing with the versatility of direct-write lithog. The technol., which we coin "SLEDGE", features dot-shaped gates that are patterned simultaneously on one topog. plane and subsequently connected by vias to interconnect metal lines. The process design enables nontrivial layouts as well as flexibility in gate dimensions, material selection, and addnl. device features such as for rf qubit control. We show that the SLEDGE process has reduced electrostatic disorder with respect to traditional overlapping gate devices with lift-off metalization, and we present spin coherent exchange oscillations and single qubit blind randomized benchmarking data.
    33. 33
      Lu, T. M.; Lee, C.-H.; Huang, S.-H.; Tsui, D. C.; Liu, C. W. Upper limit of two-dimensional electron density in enhancement-mode Si/SiGe heterostructure field-effect transistors. Appl. Phys. Lett. 2011, 99, 153510,  DOI: 10.1063/1.3652909
      33
      Upper limit of two-dimensional electron density in enhancement-mode Si/SiGe heterostructure field-effect transistors
      Lu, T. M.; Lee, C.-H.; Huang, S.-H.; Tsui, D. C.; Liu, C. W.
      Applied Physics Letters (2011), 99 (15), 153510/1-153510/3CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
      We present our study of the max. electron d., nmax, accessible via low-temp. transport expts. in enhancement-mode Si/Si1-xGex heterostructure field-effect transistors. Nmax is much higher than the value obtained from self-consistent Schroedinger-Poisson simulations and that nmax can be changed only by changing the Ge concn. in the Si1-xGex barrier layer, not by varying the barrier layer thickness. The discrepancy between expts. and simulations is explained by a non-thermal-equil. tunneling-limited model. (c) 2011 American Institute of Physics.
    34. 34
      Huang, C.-T.; Li, J.-Y.; Chou, K. S.; Sturm, J. C. Screening of remote charge scattering sites from the oxide/silicon interface of strained Si two-dimensional electron gases by an intermediate tunable shielding electron layer. Appl. Phys. Lett. 2014, 104, 243510,  DOI: 10.1063/1.4884650
      34
      Screening of remote charge scattering sites from the oxide/silicon interface of strained Si two-dimensional electron gases by an intermediate tunable shielding electron layer
      Huang, Chiao-Ti; Li, Jiun-Yun; Chou, Kevin S.; Sturm, James C.
      Applied Physics Letters (2014), 104 (24), 243510/1-243510/4CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
      We report the strong screening of the remote charge scattering sites from the oxide/semiconductor interface of buried enhancement-mode undoped Si two-dimensional electron gases (2DEGs), by introducing a tunable shielding electron layer between the 2DEG and the scattering sites. When a high d. of electrons in the buried silicon quantum well exists, the tunneling of electrons from the buried layer to the surface quantum well can lead to the formation of a nearly immobile surface electron layer. The screening of the remote charges at the interface by this newly formed surface electron layer results in an increase in the mobility of the buried 2DEG. Furthermore, a significant decrease in the min. mobile electron d. of the 2DEG occurs as well. Together, these effects can reduce the increased detrimental effect of interface charges as the setback distance for the 2DEG to the surface is reduced for improved lateral confinement by top gates. (c) 2014 American Institute of Physics.
    35. 35
      Laroche, D.; Huang, S. H.; Nielsen, E.; Chuang, Y.; Li, J.-Y.; Liu, C. W.; Lu, T. M. Scattering mechanisms in shallow undoped Si/SiGe quantum wells. AIP Advances 2015, 5, 107106,  DOI: 10.1063/1.4933026
      35
      Scattering mechanisms in shallow undoped Si/SiGe quantum wells
      Laroche, D.; Huang, S.-H.; Nielsen, E.; Chuang, Y.; Li, J.-Y.; Liu, C. W.; Lu, T. M.
      AIP Advances (2015), 5 (10), 107106/1-107106/10CODEN: AAIDBI; ISSN:2158-3226. (American Institute of Physics)
      We report the magneto-transport study and scattering mechanism anal. of a series of increasingly shallow Si/SiGe quantum wells with depth ranging from ∼ 100 nm to ∼ 10 nm away from the heterostructure surface. The peak mobility increases with depth, suggesting that charge centers near the oxide/semiconductor interface are the dominant scattering source. The power-law exponent of the electron mobility vs. d. curve, μ .varies. nα, is extd. as a function of the depth of the Si quantum well. At intermediate densities, the power-law dependence is characterized by α ∼ 2.3. At the highest achievable densities in the quantum wells buried at intermediate depth, an exponent α ∼ 5 is obsd. We propose and show by simulations that this increase in the mobility dependence on the d. can be explained by a non-equil. model where trapped electrons smooth out the potential landscape seen by the two-dimensional electron gas. (c) 2015 American Institute of Physics.
    36. 36
      Su, Y.-H.; Chuang, Y.; Liu, C.-Y.; Li, J.-Y.; Lu, T.-M. Effects of surface tunneling of two-dimensional hole gases in undoped Ge/GeSi heterostructures. Physical Review Materials 2017, 1, 044601,  DOI: 10.1103/PhysRevMaterials.1.044601
      36
      Effects of surface tunneling of two-dimensional hole gases in undoped Ge/GeSi heterostructures
      Su, Yi-Hsin; Chuang, Yen; Liu, Chia-You; Li, Jiun-Yun; Lu, Tzu-Ming
      Physical Review Materials (2017), 1 (4), 044601/1-044601/6CODEN: PRMHBS; ISSN:2475-9953. (American Physical Society)
      We investigate the effect of surface tunneling on charge distributions of two-dimensional hole gases (2DHGs) in undoped Ge/GeSi heterostructures. As in the electron channel case, the 2DHG d. sats. at a high gate voltage. As the channel depth of 2DHGs increases, a crossover of charge distributions in the system from equil. to nonequil. is obsd. at a depth of∼50 nm. A surface tunneling model is proposed to explain the d. crossover. Magnetotransport anal. is performed to investigate the limiting scattering mechanisms. The power law dependence of mobility on d. suggests that the dominant scattering mechanisms for the shallow- and deep-channel 2DHGs are remote impurity and background impurity scattering, resp. Clear quantum Hall plateaus and vanishing longitudinalmagnetoresistance are obsd. in the2DHGdevice of channels as shallow as 9 nm.
    37. 37
      Chou, K.-Y.; Hsu, N.-W.; Su, Y.-H.; Chou, C.-T.; Chiu, P.-Y.; Chuang, Y.; Li, J.-Y. Temperature dependence of dc transport characteristics for a two-dimensional electron gas in an undoped Si/SiGe heterostructure. Appl. Phys. Lett. 2018, 112, 083502,  DOI: 10.1063/1.5018636
      37
      Temperature dependence of DC transport characteristics for a two-dimensional electron gas in an undoped Si/SiGe heterostructure
      Chou, Kuan-Yu; Hsu, Nai-Wen; Su, Yi-Hsin; Chou, Chung-Tao; Chiu, Po-Yuan; Chuang, Yen; Li, Jiun-Yun
      Applied Physics Letters (2018), 112 (8), 083502/1-083502/4CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
      We investigate DC characteristics of a two-dimensional electron gas (2DEG) in an undoped Si/SiGe heterostructure and its temp. dependence. An insulated-gate field-effect transistor was fabricated, and transfer characteristics were measured at 4 K-300 K. At low temps. (T < 45 K), source electrons are injected into the buried 2DEG channel first and drain current increases with the gate voltage. By increasing the gate voltage further, the current sats. followed by a neg. transconductance obsd., which can be attributed to electron tunneling from the buried channel to the surface channel. Finally, the drain current is satd. again at large gate biases due to parallel conduction of buried and surface channels. By increasing the temp., an abrupt increase in threshold voltage is obsd. at T ∼ 45 K and it is speculated that neg. charged impurities at the Al2O3/Si interface are responsible for the threshold voltage shift. At T > 45 K, the current satn. and neg. transconductance disappear and the device acts as a normal transistor. (c) 2018 American Institute of Physics.
    38. 38
      Su, Y.-H.; Chou, K.-Y.; Chuang, Y.; Lu, T.-M.; Li, J.-Y. Electron mobility enhancement in an undoped Si/SiGe heterostructure by remote carrier screening. J. Appl. Phys. 2019, 125, 235705,  DOI: 10.1063/1.5094848
      38
      Electron mobility enhancement in an undoped Si/SiGe heterostructure by remote carrier screening
      Su, Yi-Hsin; Chou, Kuan-Yu; Chuang, Yen; Lu, Tzu-Ming; Li, Jiun-Yun
      Journal of Applied Physics (Melville, NY, United States) (2019), 125 (23), 235705/1-235705/9CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)
      We investigate the effects of surface tunneling on electrostatics and transport properties of two-dimensional electron gases (2DEGs) in undoped Si/SiGe heterostructures with different 2DEG depths. By varying the gate voltage, four stages of d.-mobility dependence are identified with two d. satn. regimes obsd., which confirms that the system transitions between equil. and nonequil. Mobility is enhanced with an increasing d. at low biases and, counterintuitively, with a decreasing d. at high biases as well. The d. satn. and mobility enhancement can be semiquant. explained by a surface tunneling model in combination with a bilayer screening theory. (c) 2019 American Institute of Physics.
    39. 39
      Degli Esposti, D.; Paquelet Wuetz, B.; Fezzi, V.; Lodari, M.; Sammak, A.; Scappucci, G. Wafer-scale low-disorder 2DEG in 28Si/SiGe without an epitaxial Si cap. Appl. Phys. Lett. 2022, 120, 184003,  DOI: 10.1063/5.0088576
      39
      Wafer-scale low-disorder 2DEG in 28Si/SiGe without an epitaxial Si cap
      Degli Esposti, Davide; Paquelet Wuetz, Brian; Fezzi, Viviana; Lodari, Mario; Sammak, Amir; Scappucci, Giordano
      Applied Physics Letters (2022), 120 (18), 184003CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
      We grow 28Si/SiGe heterostructures by reduced-pressure chem. vapor deposition and terminate the stack without an epitaxial Si cap but with an amorphous Si-rich layer obtained by exposing the SiGe barrier to dichlorosilane at 500 °C. As a result,28Si/SiGe heterostructure field-effect transistors feature a sharp semiconductor/dielec. interface and support a two-dimensional electron gas with enhanced and more uniform transport properties across a 100 mm wafer. At T = 1.7 K, we measure a high mean mobility of (1.8±0.5) x 105 cm2/V s and a low mean percolation d. of (9±1) x 1010 cm-2. From the anal. of Shubnikov-de Haas oscillations at T = 190 mK, we obtain a long mean single particle relaxation time of (8.1±0.5) ps, corresponding to a mean quantum mobility and quantum level broadening of (7.5±0.6) x 104 cm2/V s and (40±3)μeV, resp., and a small mean Dingle ratio of (2.3±0.2), indicating reduced scattering from long range impurities and a low-disorder environment for hosting high-performance spin-qubits. (c) 2022 American Institute of Physics.
    40. 40
      Paquelet Wuetz, B.; Losert, M. P.; Koelling, S.; Stehouwer, L. E. A.; Zwerver, A.-M. J.; Philips, S. G. J.; Mądzik, M. T.; Xue, X.; Zheng, G.; Lodari, M.; Amitonov, S. V.; Samkharadze, N.; Sammak, A.; Vandersypen, L. M. K.; Rahman, R.; Coppersmith, S. N.; Moutanabbir, O.; Friesen, M.; Scappucci, G. Atomic fluctuations lifting the energy degeneracy in Si/SiGe quantum dots. Nat. Commun. 2022, 13, 7730,  DOI: 10.1038/s41467-022-35458-0
      40
      Atomic fluctuations lifting the energy degeneracy in Si/SiGe quantum dots
      Paquelet Wuetz, Brian; Losert, Merritt P.; Koelling, Sebastian; Stehouwer, Lucas E. A.; Zwerver, Anne-Marije J.; Philips, Stephan G. J.; Madzik, Mateusz T.; Xue, Xiao; Zheng, Guoji; Lodari, Mario; Amitonov, Sergey V.; Samkharadze, Nodar; Sammak, Amir; Vandersypen, Lieven M. K.; Rahman, Rajib; Coppersmith, Susan N.; Moutanabbir, Oussama; Friesen, Mark; Scappucci, Giordano
      Nature Communications (2022), 13 (1), 7730CODEN: NCAOBW; ISSN:2041-1723. (Nature Portfolio)
      Electron spins in Si/SiGe quantum wells suffer from nearly degenerate conduction band valleys, which compete with the spin degree of freedom in the formation of qubits. Despite attempts to enhance the valley energy splitting deterministically, by engineering a sharp interface, valley splitting fluctuations remain a serious problem for qubit uniformity, needed to scale up to large quantum processors. Here, we elucidate and statistically predict the valley splitting by the holistic integration of 3D at.-level properties, theory and transport. We find that the concn. fluctuations of Si and Ge atoms within the 3D landscape of Si/SiGe interfaces can explain the obsd. large spread of valley splitting from measurements on many quantum dot devices. Against the prevailing belief, we propose to boost these random alloy compn. fluctuations by incorporating Ge atoms in the Si quantum well to statistically enhance valley splitting.
    41. 41
      Ershov, M.; Saxena, S.; Karbasi, H.; Winters, S.; Minehane, S.; Babcock, J.; Lindley, R.; Clifton, P.; Redford, M.; Shibkov, A. Dynamic recovery of negative bias temperature instability in p-type metal–oxide–semiconductor field-effect transistors. Appl. Phys. Lett. 2003, 83, 1647,  DOI: 10.1063/1.1604480
      41
      Dynamic recovery of negative bias temperature instability in p-type metal-oxide-semiconductor field-effect transistors
      Ershov, M.; Saxena, S.; Karbasi, H.; Winters, S.; Minehane, S.; Babcock, J.; Lindley, R.; Clifton, P.; Redford, M.; Shibkov, A.
      Applied Physics Letters (2003), 83 (8), 1647-1649CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
      An unexpected phys. phenomenon - dynamic recovery of neg. bias temp. instability (NBTI) - is reported. NBTI degrdn. in p-type MOSFET transistors is significantly (by ∼40%) reduced after stress interruption. NBTI recovery dynamics includes a very fast transient (seconds time scale) followed by a slow (tens of minutes) transient, which tends to sat. Under subsequent application of stress bias, the degrdn. quickly returns to its previous state. Thus, apparent NBTI degrdn. includes permanent and reversible components. NBTI degrdn. and device lifetime depend strongly on the measurement procedure and equipment due to these relaxation phenomena, which should be taken into account in analyzing the results of NBTI measurements.
    42. 42
      Kaczer, B.; Grasser, T.; Roussel, J.; J., Martin-Martinez; R., O’Connor; O’Sullivan, B. J.; Groeseneken, G. Ubiquitous relaxation in BTI stressing─new evaluation and insights, in 2008 IEEE International Reliability Physics Symposium , 2008; pp 20– 27.
      There is no corresponding record for this reference.
    43. 43
      Lelis, A. J.; Green, R.; Habersat, D. B.; El, M. Basic mechanisms of threshold-voltage instability and implications for reliability testing of SiC MOSFETs. IEEE Trans. Electron Devices 2015, 62, 316,  DOI: 10.1109/TED.2014.2356172
      43
      Basic mechanisms of threshold-voltage instability and implications for reliability testing of SiC MOSFETs
      Lelis, Aivars J.; Green, Ron; Habersat, Daniel B.; El, Mooro
      IEEE Transactions on Electron Devices (2015), 62 (2), 316CODEN: IETDAI; ISSN:0018-9383. (Institute of Electrical and Electronics Engineers)
      A review of the basic mechanisms affecting the stability of the threshold voltage in response to a bias-temp. stress is presented in terms of the charging and activation of near-interfacial oxide traps. An activation energy of approx. 1.1 eV was calcd. based on new exptl. results. Implications of these factors, including the recovery of some bias-temp. stress-activated defects, for improved device reliability testing are discussed.
    44. 44
      Franco, J.; Alian, A.; Kaczer, B.; Lin, D.; Ivanov, T.; Pourghaderi, A.; Martens, K.; Mols, Y.; Zhou, D.; Waldron, N.; Sioncke, S.; Kauerauf, T.; Collaert, N.; Thean, A.; Heyns, M.; Groeseneken, G. Suitability of high-k gate oxides for III–V devices: A PBTI study in In0.53Ga0.47As devices with Al2O3, in 2014 IEEE International Reliability Physics Symposium , 2014; pp 6A.2.1– 6A.2.6.
      There is no corresponding record for this reference.
    45. 45
      Neyens, S. F.; MacQuarrie, E. R.; Dodson, J. P.; Corrigan, J.; Holman, N.; Thorgrimsson, B.; Palma, M.; McJunkin, T.; Edge, L. F.; Friesen, M.; Coppersmith, S. N.; Eriksson, M. A. Measurements of capacitive coupling within a quadruple-quantum-dot array. Physical Review Applied 2019, 12, 064049,  DOI: 10.1103/PhysRevApplied.12.064049
      45
      Measurements of Capacitive Coupling Within a Quadruple-Quantum-Dot Array
      Neyens, Samuel F.; MacQuarrie, E. R.; Dodson, J. P.; Corrigan, J.; Holman, Nathan; Thorgrimsson, Brandur; Palma, M.; McJunkin, Thomas; Edge, L. F.; Friesen, Mark; Coppersmith, S. N.; Eriksson, M. A.
      Physical Review Applied (2019), 12 (6), 064049CODEN: PRAHB2; ISSN:2331-7019. (American Physical Society)
      We present measurements of the capacitive coupling energy and the interdot capacitances in a linear quadruple-quantum-dot array in undoped Si/SiGe. With the device tuned to a regime of strong (>1GHz) intra-double-dot tunnel coupling, as is typical for double-dot qubits, we measure a capacitive coupling energy of 20.9±0.3GHz. In this regime, we demonstrate a fitting procedure to ext. all the parameters in the four-dimensional Hamiltonian for two capacitively coupled charge qubits from a two-dimensional slice through the quadruple-dot charge-stability diagram. We also investigate the tunability of the capacitive coupling energy, using interdot barrier gate voltages to tune the inter- and intra-double-dot capacitances, and change the capacitive coupling energy of the double dots over a range of 15-32 GHz. We provide a model for the capacitive coupling energy based on the electrostatics of a network of charge nodes joined by capacitors, which shows how the coupling energy should depend on inter-double-dot and intra-double-dot capacitances in the network, and find that the expected trends agree well with the measurements of coupling energy.
    46. 46
      Takeda, K.; Noiri, A.; Nakajima, T.; Yoneda, J.; Kobayashi, T.; Tarucha, S. Quantum tomography of an entangled three-qubit state in silicon. Nat. Nanotechnol. 2021, 16, 965,  DOI: 10.1038/s41565-021-00925-0
      46
      Quantum tomography of an entangled three-qubit state in silicon
      Takeda, Kenta; Noiri, Akito; Nakajima, Takashi; Yoneda, Jun; Kobayashi, Takashi; Tarucha, Seigo
      Nature Nanotechnology (2021), 16 (9), 965-969CODEN: NNAABX; ISSN:1748-3387. (Nature Portfolio)
      Quantum entanglement is a fundamental property of coherent quantum states and an essential resource for quantum computing1. In large-scale quantum systems, the error accumulation requires concepts for quantum error correction. A first step toward error correction is the creation of genuinely multipartite entanglement, which has served as a performance benchmark for quantum computing platforms such as superconducting circuits2,3, trapped ions4 and nitrogen-vacancy centers in diamond5. Among the candidates for large-scale quantum computing devices, silicon-based spin qubits offer an outstanding nanofabrication capability for scaling-up. Recent studies demonstrated improved coherence times6-8, high-fidelity all-elec. control9-13, high-temp. operation14,15 and quantum entanglement of two spin qubits9,11,12. Here we generated a three-qubit Greenberger-Horne-Zeilinger state using a low-disorder, fully controllable array of three spin qubits in silicon. We performed quantum state tomog.16 and obtained a state fidelity of 88.0%. The measurements witness a genuine Greenberger-Horne-Zeilinger class quantum entanglement that cannot be sepd. into any biseparable state. Our results showcase the potential of silicon-based spin qubit platforms for multiqubit quantum algorithms.
    47. 47
      Goetzberger, A.; Heine, V.; Nicollian, E. H. Surface states in silicon from charge in the oxide coating. Appl. Phys. Lett. 1968, 12, 95,  DOI: 10.1063/1.1651913
      47
      Surface states in silicon from charges in the oxide coating
      Goetzberger, Adolf; Heine, Volker; Nicollian, Edward H.
      Applied Physics Letters (1968), 12 (3), 95-7CODEN: APPLAB; ISSN:0003-6951.
      The exptl. observed distribution of surface state d. vs. energy is correlated with the existence of Coulombic centers in the oxide. Such charges induce peaks in surface state d. near the band edges; deeper levels are introduced by 2 charges in close proximity. 13 references.
    48. 48
      Poindexter, E. H.; Caplan, P. J. Electron spin resonance of inherent and process induced defects near the Si/SiO2 interface of oxidized silicon wafers. Journal of Vacuum Science & Technology A 1988, 6, 1352,  DOI: 10.1116/1.575701
      48
      Electron spin resonance of inherent and process induced defects near the silicon/silica interface of oxidized silicon wafers
      Poindexter, Edward H.; Caplan, Philip J.
      Journal of Vacuum Science & Technology, A: Vacuum, Surfaces, and Films (1988), 6 (3, Pt. 2), 1352-7CODEN: JVTAD6; ISSN:0734-2101.
      Major point defects, inherent and process induced, near the Si/SiO2 interface of MOS structures were identified by ESR. The most pervasive defect is the Pb center, a trivalent Si atom bonded to the Si at the interface, with dangling orbital aimed into the SiO2 (e.g., Si≡Si3). The Pb orbital is the source of ∼1/2 of the elec. interface traps (d. Dit) in as-oxidized or radiation- or injection-damaged Si. Concn. of Pb is dependent on oxidn. and other thermal treatments, and is a sensitive gauge of interface physicochem. disposition. Radiationlike processing methods 〈ion implantation, rapid thermal annealing, plasma etching, and electron-beam lithog.〉 generate addnl. point defects, including charged E' centers (O3≡Si•...+Si≡O3), nonbridging oxygen hole centers O3≡Si-O•...H-O-Si≡O3), peroxy radicals (O3≡Si-O-O•...Si≡O3) in the oxide, and D centers (•Si≡Si3)n in the Si. Subsequent thermochem. treatments yield results similar to those obsd. for bulk fused SiO2 defects, but with some unresolved differences. The stability or hardness of Si/SiO2 devices appears to be related to initial defects, despite apparent anneal by thermal processing stages. A no. of studies to define the detailed physicochem. behavior of these potentially troublesome defects are now in progress.
    49. 49
      Lenahan, P. M.; Conley, J. F., Jr. What can electron paramagnetic resonance tell us about the Si/SiO2 system?. Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 1998, 16, 2134,  DOI: 10.1116/1.590301
      There is no corresponding record for this reference.
    50. 50
      Stesmans, A.; Nguyen Hoang, T.; Afanas’ev, V. V. Hydrogen interaction kinetics of Ge dangling bonds at the Si0.25Ge0.75/SiO2 interface. J. Appl. Phys. 2014, 116, 044501,  DOI: 10.1063/1.4880739
      50
      Hydrogen interaction kinetics of Ge dangling bonds at the Si0.25Ge0.75/SiO2 interface
      Stesmans, A.; Nguyen Hoang, T.; Afanas'ev, V. V.
      Journal of Applied Physics (Melville, NY, United States) (2014), 116 (4), 044501/1-044501/16CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)
      The hydrogen interaction kinetics of the GePb1 defect, previously identified by ESR as an interfacial Ge dangling bond (DB) defect occurring in densities ∼7 × 1012 cm-2 at the SiGe/SiO2 interfaces of condensation grown (100)Si/a-SiO2/Ge0.75Si0.25/a-SiO2 structures, was studied as function of temp. This was carried out, both in the isothermal and isochronal mode, through defect monitoring by capacitance-voltage measurements in conjunction with ESR probing, where it was previously demonstrated the defects to operate as neg. charge traps. The work entails a full interaction cycle study, comprised of anal. of both defect passivation (pictured as GePb1-H formation) in mol. hydrogen (∼1 atm) and reactivation (GePb1-H dissocn.) in vacuum. Both processes can be suitably described sep. by the generalized simple thermal (GST) model, embodying a 1st order interaction kinetics description based on the basic chem. reactions GePb1 + H2 → GePb1H + H and GePb1H → GePb1 + H, which are characterized by the av. activation energies Ef = 1.44 ± 0.04 eV and Ed = 2.23 ± 0.04 eV, and attendant, assumedly Gaussian, spreads σEf = 0.20 ± 0.02 eV and σEd = 0.15 ± 0.02 eV, resp. The substantial spreads refer to enhanced interfacial disorder. Combination of the sep. inferred kinetic parameters for passivation and dissocn. results in the unified realistic GST description that incorporates the simultaneous competing action of passivation and dissocn., and which is found to excellently account for the full cycle data. For process times ta ∼ 35 min, even for the optimum treatment temp. ∼380°, only ∼60% of the GePb1 system can be elec. silenced, still far remote from device grade level. This ineffectiveness is concluded, for the major part, to be a direct consequence of the excessive spreads in the activation energies, ∼2-3 times larger than for the Si DB Pb defects at the std. thermal (111)Si/SiO2 interface which may be easily passivated to device grade levels, strengthened by the reduced difference between the av. Ef and Ed values. Exploring the guidelines of the GST model indicates that passivation can be improved by decreasing Tan and attendant enlarging of ta, however, at best still leaving ∼2% defects unpassivated even for unrealistically extended anneal times. The av. dissocn. energy Ed ∼ 2.23 eV, concluded as representing the GePb1-H bond strength, is smaller than the SiPb-H one, characterized by Ed ∼ 2.83 eV. An energy deficiency is encountered regarding the energy sum rule inherent to the GST-model, the origin of which is substantiated to lie with a more complex nature of the forward passivation process than basically depicted in the GST model. The results are discussed within the context of theor. considerations on the passivation of interfacial Ge DBs by hydrogen. (c) 2014 American Institute of Physics.
    51. 51
      Kerber, A.; Cartier, E.; Groeseneken, G.; Maes, H. E.; Schwalke, U. Stress induced charge trapping effects in SiO2/Al2O3 gate stacks with TiN electrodes. J. Appl. Phys. 2003, 94, 6627,  DOI: 10.1063/1.1621718
      51
      Stress-induced charge trapping effects in SiO2/Al2O3 gate stacks with TiN electrodes
      Kerber, A.; Cartier, E.; Groeseneken, G.; Maes, H. E.; Schwalke, U.
      Journal of Applied Physics (2003), 94 (10), 6627-6630CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)
      Strong polarity dependent charge trapping effects have been obsd. in as-deposited SiO2/Al2O3 gate stacks with TiN gate electrodes on n- and p-type Si substrates using current-voltage (I-V) and capacitance-voltage (C-V) sensing techniques. For substrate injection, electron trapping occurs mainly in the bulk of the Al2O3, resulting in pos. voltage shifts for both I-V and C-V measurements. In the case of gate injection, pos. charge trapping near the SiO2/Al2O3 interface leads to neg. voltage shifts for C-V and pos. shifts for I-V measurements. The polarity-dependent charging effects are explained in terms of the difference in barrier height for substrate and gate injection and of the inherent asymmetry of the dual layer gate dielec.
    52. 52
      Pioro-Ladrière, M.; Davies, J. H.; Long, A. R.; Sachrajda, A. S.; Gaudreau, L.; Zawadzki, P.; Lapointe, J.; Gupta, J.; Wasilewski, Z.; Studenikin, S. Origin of switching noise in GaAsAlx/Ga1-xAs lateral gated devices. Phys. Rev. B 2005, 72, 115331,  DOI: 10.1103/PhysRevB.72.115331
      52
      Origin of switching noise in GaAs/AlxGa1-xAs lateral gated devices
      Pioro-Ladriere, M.; Davies, John H.; Long, A. R.; Sachrajda, A. S.; Gaudreau, Louis; Zawadzki, P.; Lapointe, J.; Gupta, J.; Wasilewski, Z.; Studenikin, S.
      Physical Review B: Condensed Matter and Materials Physics (2005), 72 (11), 115331/1-115331/8CODEN: PRBMDO; ISSN:1098-0121. (American Physical Society)
      We have studied switching (telegraph) noise at low temp. in GaAs/AlxGa1-xAs heterostructures with lateral gates and introduced a model for its origin, which explains why noise can be suppressed by cooling samples with a pos. bias on the gates. The noise was measured by monitoring the conductance fluctuations around e2/h on the first step of a quantum point contact at around 1.2 K. Cooling with a pos. bias on the gates dramatically reduces this noise, while an asym. bias exacerbates it. Our model is that the noise originates from a leakage current of electrons that tunnel through the Schottky barrier under the gate into the conduction band and become trapped near the active region of the device. The key to reducing noise is to keep the barrier opaque under exptl. conditions. Cooling with a pos. bias on the gates reduces the d. of ionized donors. This builds in an effective neg. gate voltage so that a smaller neg. bias is needed to reach the desired operating point. This suppresses tunneling from the gate and hence the noise. The redn. in the d. of ionized donors also strengthens the barrier to tunneling at a given applied voltage. Further support for the model comes from our direct observation of the leakage current into a closed quantum dot, around 10-20 A for this device. The current was detected by a neighboring quantum point contact, which showed monotonic steps in time assocd. with the tunneling of single electrons into the dot. If asym. gate voltages are applied, our model suggests that the noise will increase as a consequence of the more neg. gate voltage applied to one of the gates to maintain the same device conductance. We observe exactly this behavior in our expts.
    53. 53
      Sze, S. M.; Ng, K. K. Physics of Semiconductor Devices; Wiley: 2006; pp 484– 486.
      There is no corresponding record for this reference.
    54. 54
      Vanheusden, K.; Warren, W. L.; Fleetwood, D. M.; Schwank, J. R.; Shaneyfelt, M. R.; Draper, B. L.; Winokur, P. S.; Devine, R. A. B.; Archer, L. B.; Brown, G. A.; Wallace, R. M. Chemical kinetics of mobile-proton generation and annihilation in SiO2 thin films. Appl. Phys. Lett. 1998, 73, 674,  DOI: 10.1063/1.121944
      54
      Chemical kinetics of mobile-proton generation and annihilation in SiO2 thin films
      Vanheusden, K.; Warren, W. L.; Fleetwood, D. M.; Schwank, J. R.; Shaneyfelt, M. R.; Draper, B. L.; Winokur, P. S.; Devine, R. A. B.; Archer, L. B.; Brown, G. A.; Wallace, R. M.
      Applied Physics Letters (1998), 73 (5), 674-676CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
      The chem. kinetics of mobile-proton reactions in the SiO2 film of Si/SiO2/Si structures were analyzed as a function of forming-gas anneal parameters in the 300-600° temp. range. The authors' data show that the initial buildup of mobile protons is limited by the rate of lateral H diffusion into the SiO2 films. The final d. of mobile protons is detd. by the cooling rate which terminates the annealing process and, in the case of subsequent anneals, by the temp. of the final anneal. To explain the observations, the authors propose a dynamical equil. model which assumes a reversible interfacial reaction with a temp.-dependent balance.
    55. 55
      Hoffmann, K. System Integration: From Transistor Design to Large Scale Integrated Circuits; Wiley: 2004; pp 339– 340 and 345– 352.
      There is no corresponding record for this reference.
    56. 56
      Meyer, M.; Déprez, C.; van Abswoude, T. R.; Meijer, I. N.; Liu, D.; Wang, C.; Karwal, S.; Oosterhout, S.; Borsoi, F.; Sammak, A.; Hendrickx, N. W.; Scappucci, G.; Veldhorst, M. Dataset underlying the manuscript: Electrical control of uniformity in quantum dot devices. Zenodo.org , 2022.
      There is no corresponding record for this reference.

  • Supporting Information

    Supporting Information

    The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acs.nanolett.2c04446.

    • Materials and device fabrication details, description of the experimental setup, details on the experimental procedures, SEM images of devices nominally identical with those used in this work, presentation of ten consecutive hysteresis cycles, hysteresis cycles obtained in Ge/SiGe single hole transistor structures, full schematics of the stress voltage sequence employed for tuning the plunger gate pinch-off voltages in a linear array, stability of the four plunger pinch-off characteristics after the tuning procedure presented, analysis of the effect of stress voltages on coulomb-blockade oscillations, table of samples investigated and corresponding reversal points (PDF)


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