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Functional Inorganic Materials and Devices

Flexible p-Type WSe2 Transistors with Alumina Top-Gate Dielectric
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  • Quỳnh Thị Phùng
    Quỳnh Thị Phùng
    Chair of Electronic Devices, RWTH Aachen University, 52074 Aachen, Germany
    Sensors Laboratory, Department of Microsystems Engineering, University of Freiburg, 79110 Freiburg, Germany
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  • Lukas Völkel
    Lukas Völkel
    Chair of Electronic Devices, RWTH Aachen University, 52074 Aachen, Germany
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    Orcidhttps://orcid.org/0000-0002-8138-9980
  • Agata Piacentini
    Agata Piacentini
    Chair of Electronic Devices, RWTH Aachen University, 52074 Aachen, Germany
    AMO GmbH, Adv. Microelectron. Cent. Aachen, 52074 Aachen, Germany
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    Orcidhttps://orcid.org/0000-0003-1368-0511
  • Ardeshir Esteki
    Ardeshir Esteki
    Chair of Electronic Devices, RWTH Aachen University, 52074 Aachen, Germany
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  • Annika Grundmann
    Annika Grundmann
    Compound Semiconductor Technology, RWTH Aachen University, 52074 Aachen, Germany
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  • Holger Kalisch
    Holger Kalisch
    Compound Semiconductor Technology, RWTH Aachen University, 52074 Aachen, Germany
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  • Michael Heuken
    Michael Heuken
    Compound Semiconductor Technology, RWTH Aachen University, 52074 Aachen, Germany
    AIXTRON SE, 52134 Herzogenrath, Germany
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  • Andrei Vescan
    Andrei Vescan
    Compound Semiconductor Technology, RWTH Aachen University, 52074 Aachen, Germany
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    Orcidhttps://orcid.org/0000-0001-9465-2621
  • Daniel Neumaier
    Daniel Neumaier
    AMO GmbH, Adv. Microelectron. Cent. Aachen, 52074 Aachen, Germany
    Bergische Universität Wuppertal, 42119 Wuppertal, Germany
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  • Max C. Lemme
    Max C. Lemme
    Chair of Electronic Devices, RWTH Aachen University, 52074 Aachen, Germany
    AMO GmbH, Adv. Microelectron. Cent. Aachen, 52074 Aachen, Germany
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    Orcidhttps://orcid.org/0000-0003-4552-2411
  • Alwin Daus*
    Alwin Daus
    Chair of Electronic Devices, RWTH Aachen University, 52074 Aachen, Germany
    Sensors Laboratory, Department of Microsystems Engineering, University of Freiburg, 79110 Freiburg, Germany
    *Email [email protected]
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    Orcidhttps://orcid.org/0000-0001-7461-3756
Open PDFSupporting Information (1)

ACS Applied Materials & Interfaces

Cite this: ACS Appl. Mater. Interfaces 2024, 16, 44, 60541–60547
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https://doi.org/10.1021/acsami.4c13296
Published October 25, 2024

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Abstract

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Tungsten diselenide (WSe2) field-effect transistors (FETs) are promising for emerging electronics because of their tunable polarity, enabling complementary transistor technology, and their suitability for flexible electronics through material transfer. In this work, we demonstrate flexible p-type WSe2 FETs with absolute drain currents |ID| up to 7 μA/μm. We achieve this by fabricating flexible top-gated FETs with a combined WSe2 and metal contact transfer approach using WSe2 grown by metal–organic chemical vapor deposition on sapphire. Despite moderate WSe2 crystal grain size, our devices show similar or higher |ID| and ID on/off ratio (∼105) compared to most devices with exfoliated single-crystal WSe2 from the literature. We analyze charge trapping in our devices using pulsed and bias stress measurements. Notably, the high |ID| values are preserved during pulsing, where charge trapping is minimized. Overall, we demonstrate a fabrication approach advantageous for high drain currents in flexible 2D transistors.

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1. Introduction

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Traditionally, electronic devices and circuits are rigid, which limits their application in various fields. Flexible electronics have gained increased attention due to their ability to conform to unconventional shapes and surfaces, expanding their potential applications to fields such as wearable technology, medical devices, and flexible displays. Two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDs) are of interest for transistors with low power consumption because their large bandgaps (up to ∼2.2 eV) enable low off-currents (∼fA μm–1). (1,2) Furthermore, TMDs are among the most promising materials for high-performance flexible electronics due to their superior scaling behavior and high carrier mobility up to ∼150 cm2 V–1 s–1. (3−5)
Molybdenum disulfide (MoS2) has been one of the most investigated 2D semiconductors, but p-type transistors are difficult to obtain with MoS2. In contrast, tungsten diselenide (WSe2)-based devices have shown more promise for 2D complementary metal oxide semiconductor (CMOS) technology by offering both p-type and n-type operation. (6,7) High-quality large-area 2D material growth and residue-free transfer onto flexible substrates are crucial to implement 2D materials into high-performance flexible CMOS electronics.
In this article, we demonstrate high-performance flexible p-type field-effect transistors (FETs) using few-layer WSe2 grown by metal–organic chemical vapor deposition (MOCVD). This indicates that our gentle material transfer (TMD and source/drain contacts embedded in polyimide) avoids damage to the channel, and the device architecture is favorable for high drain currents. (8) Our flexible WSe2 transistors reach absolute drain currents |ID| of up to 7 μA/μm, an extrinsic field-effect mobility μFE,ext up to 12 cm2 V–1 s–1, and an ID on/off ratio over 105, all of which are competitive with other works using exfoliated single-crystal WSe2. (9−12) We also carefully evaluate the charge trapping behavior in our WSe2 FETs with top-gate alumina dielectrics through bias stress and pulsed measurements. The results corroborate good drain currents as an indication of preserved channel quality. However, we also conclude that the alumina top-gate dielectric still needs improvement in future work. Overall, our results highlight the high potential of flexible p-type WSe2 transistors which offer a promising outlook for the realization of flexible complementary electronics. (4)

2. Experimental Section

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The fabrication of flexible FETs is described in Figure 1a. The first fabrication steps were performed on the sapphire growth substrate, on which a continuous polycrystalline few-layer WSe2 film was grown by MOCVD. (13) First, the Pd source/drain electrodes were deposited by electron-beam evaporation and structured by lift-off. Then, 5 μm polyimide (PI) was spin-coated on top, and the entire stack, including WSe2, was transferred in deionized water. After transfer, the PI was flipped and used as the flexible substrate. Then, the device fabrication was continued by patterning WSe2 via dry etching using an Al hard mask. The device fabrication was completed by depositing the alumina dielectric and the Pd top-gate via atomic-layer deposition and electron-beam evaporation, respectively. Finally, the source/drain contact holes were opened by wet etching of alumina for electrical measurements. More details on the fabrication process are described in Supporting Information Section 1. We note that 2D TMD devices on such thin substrates are also bendable at least to the millimeter range, as has previously been confirmed. (8,12,14,15) This is because bending strain is effectively minimized by reduction of substrate thickness d according to strain = d/2r, where r is the bending radius. (8) Figure 1b displays optical images of the film with contacts and unpatterned WSe2 on sapphire (before transfer) and on PI (after transfer). Before transfer, the Pd contacts were placed on top of TMDs. After transfer the stack is flipped, i.e., WSe2 is on top, and the Pd contacts are embedded below within the PI substrate. Figure 1c displays the Raman spectra of WSe2 before and after transfer, measured on sapphire and on PI. The E peaks before and after transfer are 249 and 248.8 cm–1, confirming the successful transfer of WSe2. The minor shift in the Raman E peak of about −0.2 cm–1 can be attributed to a small change in strain upon transfer from sapphire. (16,17) Figure 1d displays an atomic force microscopy (AFM) image of as-grown WSe2 revealing its polycrystalline nature with grain sizes on the order of several hundred nanometers. An AFM height profile determining a WSe2 thickness of ∼3 nm and a scanning electron microscopy image of the WSe2 film are available in Figure S1a–c. Figure 1e displays an optical image of the flexible PI after device fabrication.

Figure 1

Figure 1. Fabrication process of flexible WSe2 FETs. (a) Fabrication process flow of flexible top-gated WSe2 transistors. (b) Optical images of WSe2 film with contacts before transfer on sapphire and after transfer on PI. (c) Raman spectra of as-grown WSe2 on sapphire and after transfer on PI. (d) Atomic force microscopy image of the as-grown WSe2. (e) Optical image of the flexible PI substrate after fabrication.

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3. Results and Discussion

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The device cross section is schematically illustrated in Figure 2a. The devices have a staggered architecture, where the channel is sandwiched between the source/drain and the gate, and a lateral overlap between these electrodes exists. Figure 2b displays an optical image of flexible WSe2 FETs with different channel lengths ranging from 2 to 10 μm and one common gate electrode. The transfer characteristic of the device with the highest ID on/off ratio (>105) is displayed in Figure 2c showing reasonable switching behavior, low gate current IG, and p-type characteristic. The corresponding output characteristics can be found in Figure S1d. Figure 2d shows the transfer characteristics of the device with the highest |ID| = 7 μA/μm at drain–source voltage VDS = −1 V. The μFE,ext of this device is 12.2 cm2 V–1 s–1, extracted at VDS = −0.1 V with a measured gate capacitance density of Cox ≈ 0.314 μF cm–2 (Supporting Information Section 2).

Figure 2

Figure 2. Flexible p-type WSe2 devices. (a) Schematic device cross section. (b) Optical image of flexible FETs. Unlabeled contacts correspond to source/drain to measure channels. (c, d) Transfer characteristics of devices showing the highest ID on/off ratio in (c) and highest drain current |ID| in (d), including the corresponding gate leakage currents |IG|. (e, f) Benchmarking of flexible p-type WSe2 FETs comparing maximum |ID|, ID on/off ratio, and L. This work’s data are for |ID| at VDS = −1 V, and the values from others are indicated (see also Table S1).

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Comparing our best device parameters to recent literature, we find that they are overall comparable to demonstrations of p-type FETs with MOCVD WSe2 channels on rigid substrates, which achieved |ID| up to ∼15–20 μA/μm with channel lengths <500 nm, ID on/off ratio ≥105, and hole mobility up to ∼11 cm2 V–1 s–1. (18,19) So far, there have only been few reports on flexible p-type WSe2 transistors. Pu et al. reported a drain current |ID| = 6.18 μA at VDS = −0.1 V and an ID on/off ratio of ∼2 × 103 using ion gel as a gate electrolyte. (20) Piacentini et al. used the same WSe2 material source as us but employed a different fabrication process, reporting |ID| = 0.0186 μA/μm at VDS = −1 V, with an ID on/off ratio ∼9 × 104. (21) A very recently published work using exfoliated WSe2 channels and h-BN as gate dielectric reported |ID| ≈ 7.6 μA/μm at VDS = 1 V, with an ID on/off ratio ∼108. (12) A comparison with further works using exfoliated WSe2 material (9−11) is presented in Table S1. Figure 2e,f display benchmarking of our flexible WSe2 transistors compared to other works. (9−12,21) Figure 2e compares the drain current |ID| and ID on/off ratio of flexible p-type WSe2 FETs, demonstrating the good performance of our devices and highlighting that we achieve higher |ID| compared to most other works. Figure 2f displays the maximum |ID| versus the channel length L. Overall, the benchmarking shows that our devices with polycrystalline WSe2 material can outperform devices even with a monocrystalline exfoliated material. This signifies the importance of a carefully crafted fabrication approach and device architecture that enables high drain currents (i.e., the staggered architecture, Figure 2a, as described above). Our data further hint at a possible increase of variability in devices with shorter L, which could be related to the grain sizes and relative thickness variations in our material. (22−24) This is visible in our data set of 16 devices showing our device parameter statistics (Figure S2), but we note that for stronger conclusions on variability, a larger data set will be necessary.
Next, we conducted gate bias stress (BS) measurements to investigate the properties of the alumina top-gate dielectric. We applied negative BS at a gate-source voltage VGS = −5 V with different cumulative stress times t and measured transfer characteristic curves consecutively as shown in Figure 3a. After negative BS, |ID| increases and the threshold voltage (VT) of the device shifts in the positive VGS direction (Figure 3a,b). We attribute this to charge trapping caused by charge exchange between the gate electrode and the dielectric: Negative charges under negative BS hop from the gate into the dielectric causing the VT shift. This phenomenon is observable in defective dielectrics. (25−27) We note that an alternative explanation could be ion movements in the dielectrics, (28−30) but ion movement does not necessarily lead to such BS behavior. In fact, electrolyte-gated transistors have been reported to exhibit charge trapping of channel carriers, which lead to the opposite VT shift. (31,32) Furthermore, we have analyzed IG in our devices before/after BS as well as after extended recovery periods (minutes to months, see Figure S4). On the one hand, we find that the devices naturally recover from BS after 6 months of waiting aside from small remaining VT shifts (Figure S4a–d). On the other hand, we can recognize an increased positive IG at positive VGS right after BS, which then reduces in subsequent VGS sweeps and within minutes of wait time, indicating a movement of negative charges back from the dielectric into the gate electrode (Figure S4e,f). Thus, we believe that the mechanism for the BS and hysteresis behavior (as discussed further below) can be explained by charge trapping and detrapping. Moreover, we also extracted VT as a function of stress time and recovery/wait time (Figure S5). We note that the extraction accuracy of VT was limited due to strong shifts observed, but still, it shows a clear trend and also reveals a slow recovery process. Further, we confirmed that the mechanism is not caused by the WSe2 channels themselves by fabricating flexible n-type MoS2 FETs with the same process flow and subjecting them to positive BS at VGS = +5 V, which is where such n-type FETs are switched “on”. We observed the same phenomenon for such devices; i.e., VT analogously shifts negatively and ID increases upon BS as shown in Figure 3c,d (more device data in Figure S6). Interestingly, the effect is less pronounced in n-type MoS2 FETs compared to p-type WSe2 FETs, which could be related to differences in the dielectric trap energy level distributions relative to the applied VGS for electrons and holes in the respective device configurations. (33) Overall, we deduce from these results that the large VT shifts after prolonged BS indicate a high defect density in our dielectric. This is attributed to a nonoptimized ALD process which has a low deposition rate (∼0.4 Å/cycle).

Figure 3

Figure 3. Flexible TMD devices under bias stress (BS). (a) Transfer characteristics of WSe2 FET under −5 V gate BS as a function of cumulative stress time t. (b) |ID| at VGS = −5 V versus t of four WSe2 FETs. (c) Transfer characteristic of MoS2 FET under +5 V gate BS as a function of t. (d) |ID| at VGS = +5 V versus t of four MoS2 FETs.

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Finally, we verified that this BS effect, leading to an |ID| increase, does not exaggerate our extracted maximum |ID|. We did this using pulsed measurements to minimize the BS effects. The pulse widths ton were varied from 500 μs to 500 ms, with rise and fall times tR,F = 10 μs and a constant pulse-off time toff ∼ 500 ms. The measurement scheme and relevant parameters are further detailed in Figure S7 and Table S2. Figure 4a displays ID at VGS = −5 V after normalization with the shortest pulse width of 500 μs for five devices. |ID| at short pulse widths is higher than |ID| measured at direct-current (dc) conditions, confirming that we do not overestimate the maximum drain currents in dc measurements. Generally, we find that the maximum |ID| is reduced with an increasing pulse width. Figure 4b shows extracted hystereses for different pulse widths using the ΔVT values of both sweep directions of five FETs. Hysteresis is defined as the difference in VT between the backward (negative-to-positive) and forward (positive-to-negative) VGS sweeps. Negative/positive ΔVT or ΔVGS indicate clockwise/counterclockwise ID–VGS hysteresis. With short pulse widths, devices exhibit the common clockwise hysteresis behavior (negative ΔVT and ΔVGS shifts) associated with channel/dielectric interface trapping. (36−38) With long pulse widths, the charge exchange at the gate/dielectric side is stronger, leading to counterclockwise hysteresis (positive ΔVT and ΔVGS shifts). This observation points to different time constants associated with the channel/dielectric charge trapping and the gate/dielectric charge trapping, as illustrated in Figure 4c. The associated energy level values in flat-band conditions including references are presented in Figure S8. The trapped holes are likely close to the semiconductor/dielectric interface located at the interface or in border oxide traps (39,40) due to the faster time scales observed. The trapped electrons from the gate are expected to be located further away from the interface in the bulk of the dielectric, as indicated in Figure 4c, and likely contribute to a slow recovery after BS (see Figures S4 and S5). Figure 4d displays a comparison of ΔVGS at the same |ID| across a wide range of current levels of one FET. There is a transition between the two mechanisms at a pulse width of 100 ms. The transfer characteristic curves of this FET, corresponding to the data shown in Figure 4d, are displayed in Figure S9. The hysteresis ΔVGS values of other WSe2 FETs can be found in Figure S10. Lastly, we also compare the extracted μFE,ext values as a function of pulse width (Figure S11). In general, we did not observe any systematic dependence of mobility on the pulse parameters nor deviation from the dc extraction.

Figure 4

Figure 4. Pulsed measurements: (a) ID normalized by ID at a 500 μs pulse width. For the ID values at dc, VGS was applied for ∼180 ms for each voltage step (Table S2). However, the voltage vs time profiles are different for both methods (Figure S7). (b) ΔVT of five WSe2 FETs versus pulse width. (c) Band diagram showing the charge trapping from gate to dielectric and from channel to dielectric. The blue and red defect bands in Al2O3 represent dominant trapping sites for electrons and holes, respectively. (34) We note that more defect energy levels might be available for trapping across different energies, which depends also on the dielectric deposition process. (35) (d) Hysteresis ΔVGS for one WSe2 FET measured with different pulse widths.

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4. Conclusions

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In summary, we have demonstrated top-gated staggered flexible WSe2 FETs using a direct transfer approach compatible with MOCVD TMDs grown on sapphire. Our devices exhibit high |ID| up to 7 μA/μm and μFE,ext up to 12.2 cm2 V–1 s–1, with |ID| being similar to or higher than previous works using exfoliated WSe2. We thoroughly investigated the electrical properties of our devices with top-gate dielectric and analyzed the BS and hysteresis behaviors. From that we conclude that there are two competing charge trapping mechanisms present: one at the channel/dielectric interface and one from the gate to the dielectric. Overall, the results of our study highlight the promise of WSe2 for p-type FETs in flexible electronics but also underline that careful process engineering is required to leverage the full potential of available materials, e.g., regarding gate dielectrics. (33,41)

Supporting Information

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The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsami.4c13296.

  • Device fabrication, mobility extraction, additional data from bias stress and pulse measurements including hysteresis; additional SEM and AFM images and benchmarking information, device parameter statistics, capacitance measurements, data on device recovery after bias stress, additional information on measurement schemes for dc and pulsing; band diagram including references (PDF)

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Author Information

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  • Corresponding Author
  • Authors
    • Quỳnh Thị Phùng - Chair of Electronic Devices, RWTH Aachen University, 52074 Aachen, Germany;  Sensors Laboratory, Department of Microsystems Engineering, University of Freiburg, 79110 Freiburg, Germany
    • Lukas Völkel - Chair of Electronic Devices, RWTH Aachen University, 52074 Aachen, Germany;  Orcidhttps://orcid.org/0000-0002-8138-9980
    • Agata Piacentini - Chair of Electronic Devices, RWTH Aachen University, 52074 Aachen, Germany;  AMO GmbH, Adv. Microelectron. Cent. Aachen, 52074 Aachen, Germany;  Orcidhttps://orcid.org/0000-0003-1368-0511
    • Ardeshir Esteki - Chair of Electronic Devices, RWTH Aachen University, 52074 Aachen, Germany
    • Annika Grundmann - Compound Semiconductor Technology, RWTH Aachen University, 52074 Aachen, Germany
    • Holger Kalisch - Compound Semiconductor Technology, RWTH Aachen University, 52074 Aachen, Germany
    • Michael Heuken - Compound Semiconductor Technology, RWTH Aachen University, 52074 Aachen, Germany;  AIXTRON SE, 52134 Herzogenrath, Germany
    • Andrei Vescan - Compound Semiconductor Technology, RWTH Aachen University, 52074 Aachen, Germany;  Orcidhttps://orcid.org/0000-0001-9465-2621
    • Daniel Neumaier - AMO GmbH, Adv. Microelectron. Cent. Aachen, 52074 Aachen, Germany;  Bergische Universität Wuppertal, 42119 Wuppertal, Germany
    • Max C. Lemme - Chair of Electronic Devices, RWTH Aachen University, 52074 Aachen, Germany;  AMO GmbH, Adv. Microelectron. Cent. Aachen, 52074 Aachen, Germany;  Orcidhttps://orcid.org/0000-0003-4552-2411
  • Author Contributions

    Q.T.P. performed the device fabrication and characterization, L.V. contributed to stress and pulse measurements, A.P. contributed to discussions on electrical data, and A.E. contributed to capacitance measurements. A.G. and H.K. performed the MoS2 and WSe2 MOCVD. L.V. carried out AFM and SEM. Q.T.P. analyzed all data with help from A.D.; A.D. and Q.T.P. wrote the manuscript. All authors revised and commented on the manuscript. M.H. and A.V. supervised the MOCVD. A.D. supervised the overall study.

  • Funding

    We acknowledge support by the German Research Foundation through the Emmy Noether Programme (506140715) and the MOSTFLEX project (LE 2440/7-1). We also acknowledge funding by the BMBF NEUROTEC 2 project (16ME0399/16ME0400) and the EU MISEL project (101016734).

  • Notes
    The authors declare no competing financial interest.

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    Large-Area Synthesis of Highly Crystalline WSe2 Monolayers and Device Applications
    Huang, Jing-Kai; Pu, Jiang; Hsu, Chang-Lung; Chiu, Ming-Hui; Juang, Zhen-Yu; Chang, Yong-Huang; Chang, Wen-Hao; Iwasa, Yoshihiro; Takenobu, Taishi; Li, Lain-Jong
    ACS Nano (2014), 8 (1), 923-930CODEN: ANCAC3; ISSN:1936-0851. (American Chemical Society)
    The monolayer transition metal dichalcogenides have recently attracted much attention owing to their potential in valleytronics, flexible and low-power electronics, and optoelectronic devices. Recent reports demonstrated the growth of large-size two-dimensional MoS2 layers by the sulfurization of molybdenum oxides. However, the growth of a transition metal selenide monolayer has still been a challenge. Here the authors report that the introduction of hydrogen in the reaction chamber helps to activate the selenization of WO3, where large-size WSe2 monolayer flakes or thin films can be successfully grown. The top-gated field-effect transistors based on WSe2 monolayers using ionic gels as the dielecs. exhibit ambipolar characteristics, where the hole and electron mobility values are up to 90 and 7 cm2/Vs, resp. These films can be transferred onto arbitrary substrates, which may inspire research efforts to explore their properties and applications. The resistor-loaded inverter based on a WSe2 film, with a gain of ∼13, further demonstrates its applicability for logic-circuit integrations.
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  7. 7
    Ngo, T. D.; Yang, Z.; Lee, M.; Ali, F.; Moon, I.; Kim, D. G.; Taniguchi, T.; Watanabe, K.; Lee, K.; Yoo, W. J. Fermi-level Pinning Free High-performance 2D CMOS Inverter Fabricated with van Der Waals Bottom Contacts. Adv. Electron. Mater. 2021, 7 (5), 2001212,  DOI: 10.1002/aelm.202001212
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    7
    Fermi-Level Pinning Free High-Performance 2D CMOS Inverter Fabricated with Van Der Waals Bottom Contacts
    Ngo, Tien Dat; Yang, Zheng; Lee, Myeongjin; Ali, Fida; Moon, Inyong; Kim, Dong Gyu; Taniguchi, Takashi; Watanabe, Kenji; Lee, Kang-Yoon; Yoo, Won Jong
    Advanced Electronic Materials (2021), 7 (5), 2001212CODEN: AEMDBW; ISSN:2199-160X. (Wiley-VCH Verlag GmbH & Co. KGaA)
    Effective control of 2D transistors polarity is a crit. challenge in the process for integrating 2D materials into semiconductor devices. Herein, a doping-free approach for developing tungsten diselenide (WSe2) logic devices by utilizing the van der Waals (vdWs) bottom elec. contact with platinum and indium as the high and low work function metal resp. is reported. The device structure is free from chem. disorder and crystal defects arising from metal deposition, which enables a near ideal Fermi-level de-pinning. With effective controllability of device polarity through metal work function change, a complementary metal-oxide-semiconductor field effect transistor inverter with a gain of 198 at a bias voltage of 4.5 V is achieved. This study demonstrates an ultrahigh performance 2D inverter realized by controlling the device polarity from using Fermi-level pinning-free vdWs bottom contacts.
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  8. 8
    Daus, A.; Vaziri, S.; Chen, V.; Köroǧlu, Ç.; Grady, R. W.; Bailey, C. S.; Lee, H. R.; Schauble, K.; Brenner, K.; Pop, E. High-Performance Flexible Nanoscale Transistors Based on Transition Metal Dichalcogenides. Nat. Electron. 2021, 4 (7), 495– 501,  DOI: 10.1038/s41928-021-00598-6
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    8
    High-performance flexible nanoscale transistors based on transition metal dichalcogenides
    Daus, Alwin; Vaziri, Sam; Chen, Victoria; Koroglu, Cagil; Grady, Ryan W.; Bailey, Connor S.; Lee, Hye Ryoung; Schauble, Kirstin; Brenner, Kevin; Pop, Eric
    Nature Electronics (2021), 4 (7), 495-501CODEN: NEALB3; ISSN:2520-1131. (Nature Portfolio)
    Two-dimensional (2D) semiconducting transition metal dichalcogenides could be used to build high-performance flexible electronics. However, flexible field-effect transistors (FETs) based on such materials are typically fabricated with channel lengths on the micrometre scale, not benefitting from the short-channel advantages of 2D materials. Here, we report flexible nanoscale FETs based on 2D semiconductors; these are fabricated by transferring chem.-vapor-deposited transition metal dichalcogenides from rigid growth substrates together with nano-patterned metal contacts, using a polyimide film, which becomes the flexible substrate after release. Transistors based on monolayer molybdenum disulfide (MoS2) are created with channel lengths down to 60 nm and on-state currents up to 470μA μm-1 at a drain-source voltage of 1 V, which is comparable to the performance of flexible graphene and cryst. silicon FETs. Despite the low thermal cond. of the flexible substrate, we find that heat spreading through the metal gate and contacts is essential to reach such high current densities. We also show that the approach can be used to create flexible FETs based on molybdenum diselenide (MoSe2) and tungsten diselenide (WSe2).
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  9. 9
    Qiu, H.; Liu, Z.; Yao, Y.; Herder, M.; Hecht, S.; Samorì, P. Simultaneous Optical Tuning of Hole and Electron Transport in Ambipolar WSe2 Interfaced with a Bicomponent Photochromic Layer: From High-mobility Transistors to Flexible Multilevel Memories. Adv. Mater. 2020, 32 (11), 1907903,  DOI: 10.1002/adma.202070085
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  10. 10
    Shen, T.; Penumatcha, A. V.; Appenzeller, J. Strain Engineering for Transition Metal Dichalcogenides Based Field Effect Transistors. ACS Nano 2016, 10 (4), 4712– 4718,  DOI: 10.1021/acsnano.6b01149
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    10
    Strain Engineering for Transition Metal Dichalcogenides Based Field Effect Transistors
    Shen, Tingting; Penumatcha, Ashish V.; Appenzeller, Joerg
    ACS Nano (2016), 10 (4), 4712-4718CODEN: ANCAC3; ISSN:1936-0851. (American Chemical Society)
    Using elec. characteristics from three-terminal field-effect transistors (FETs), the authors demonstrate substantial strain induced band gap tunability in transition metal dichalcogenides (TMDs) in line with theor. predictions and optical expts. Devices were fabricated on flexible substrates, and a cantilever sample holder was used to apply uniaxial tensile strain to the various multilayer TMD FETs. Analyzing in particular transfer characteristics, it is argued that the modified device characteristics under strain are clear evidence of a band gap redn. of 100 meV in WSe2 under 1.35% uniaxial tensile strain at room temp. The obtained device characteristics imply that the band gap does not shrink uniformly under strain relative to a ref. potential defined by the source/drain contacts. Instead, the band gap change is only related to a change of the conduction band edge of WSe2, resulting in a decrease in the Schottky barrier (SB) for electrons without any change for hole injection into the valence band. Simulations of SB device characteristics are employed to explain this point and to quantify our findings. Last, our exptl. results are compared with DFT calcns. under strain showing excellent agreement between theor. predictions and the exptl. data presented here.
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  11. 11
    Zou, Y.; Zhang, Z.; Yan, J.; Lin, L.; Huang, G.; Tan, Y.; You, Z.; Li, P. High-Temperature Flexible WSe2 Photodetectors with Ultrahigh Photoresponsivity. Nat. Commun. 2022, 13 (1), 4372,  DOI: 10.1038/s41467-022-32062-0
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    11
    High-temperature flexible WSe2 photodetectors with ultrahigh photoresponsivity
    Zou, Yixuan; Zhang, Zekun; Yan, Jiawen; Lin, Linhan; Huang, Guanyao; Tan, Yidong; You, Zheng; Li, Peng
    Nature Communications (2022), 13 (1), 4372CODEN: NCAOBW; ISSN:2041-1723. (Nature Portfolio)
    The development of high-temp. photodetectors can be beneficial for numerous applications, such as aerospace engineering, military defense and harsh-environments robotics. However, current high-temp. photodetectors are characterized by low photoresponsivity (<10 A/W) due to the poor optical sensitivity of commonly used heat-resistant materials. Here, we report the realization of h-BN-encapsulated graphite/WSe2 photodetectors which can endure temps. up to 700°C in air (1000°C in vacuum) and exhibit unconventional neg. photocond. (NPC) at high temps. Operated in NPC mode, the devices show a photoresponsivity up to 2.2 x 106 A/W, which is ∼5 orders of magnitude higher than that of state-of-the-art high-temp. photodetectors. Furthermore, our devices demonstrate good flexibility, making it highly adaptive to various shaped surfaces. Our approach can be extended to other 2D materials and may stimulate further developments of 2D optoelectronic devices operating in harsh environments.
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  12. 12
    Ming, Z.; Sun, H.; Wang, H.; Sheng, Z.; Wang, Y.; Zhang, Z. Full Two-Dimensional Ambipolar Field-Effect Transistors for Transparent and Flexible Electronics. ACS Appl. Mater. Interfaces 2024, 16, 45131– 45138,  DOI: 10.1021/acsami.4c06602
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  13. 13
    Grundmann, A.; Beckmann, Y.; Ghiami, A.; Bui, M.; Kardynal, B.; Patterer, L.; Schneider, J.; Kummell, T.; Bacher, G.; Heuken, M.; Kalisch, H.; Vescan, A. Impact of Synthesis Temperature and Precursor Ratio on the Crystal Quality of MOCVD WSe2 Monolayers. Nanotechnology 2023, 34 (20), 205602,  DOI: 10.1088/1361-6528/acb947
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    Nassiri Nazif, K.; Daus, A.; Hong, J.; Lee, N.; Vaziri, S.; Kumar, A.; Nitta, F.; Chen, M. E.; Kananian, S.; Islam, R. High-Specific-Power Flexible Transition Metal Dichalcogenide Solar Cells. Nat. Commun. 2021, 12 (1), 7034,  DOI: 10.1038/s41467-021-27195-7
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    14
    High-specific-power flexible transition metal dichalcogenide solar cells
    Nassiri Nazif, Koosha; Daus, Alwin; Hong, Jiho; Lee, Nayeun; Vaziri, Sam; Kumar, Aravindh; Nitta, Frederick; Chen, Michelle E.; Kananian, Siavash; Islam, Raisul; Kim, Kwan-Ho; Park, Jin-Hong; Poon, Ada S. Y.; Brongersma, Mark L.; Pop, Eric; Saraswat, Krishna C.
    Nature Communications (2021), 12 (1), 7034CODEN: NCAOBW; ISSN:2041-1723. (Nature Research)
    Semiconducting transition metal dichalcogenides (TMDs) are promising for flexible high-specific-power photovoltaics due to their ultrahigh optical absorption coeffs., desirable band gaps and self-passivated surfaces. However, challenges such as Fermi-level pinning at the metal contact-TMD interface and the inapplicability of traditional doping schemes have prevented most TMD solar cells from exceeding 2% power conversion efficiency (PCE). In addn., fabrication on flexible substrates tends to contaminate or damage TMD interfaces, further reducing performance. Here, we address these fundamental issues by employing: (1) transparent graphene contacts to mitigate Fermi-level pinning, (2) MoOx capping for doping, passivation and anti-reflection, and (3) a clean, non-damaging direct transfer method to realize devices on lightwt. flexible polyimide substrates. These lead to record PCE of 5.1% and record specific power of 4.4 W g-1 for flexible TMD (WSe2) solar cells, the latter on par with prevailing thin-film solar technologies cadmium telluride, copper indium gallium selenide, amorphous silicon and III-Vs. We further project that TMD solar cells could achieve specific power up to 46 W g-1, creating unprecedented opportunities in a broad range of industries from aerospace to wearable and implantable electronics.
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  15. 15
    Piacentini, A.; Polyushkin, D. K.; Uzlu, B.; Grundmann, A.; Heuken, M.; Kalisch, H.; Vescan, A.; Wang, Z.; Lemme, M. C.; Mueller, T.; Neumaier, D. Flexible Complementary Metal-Oxide-Semiconductor Inverter Based on 2D P-type WSe2 and N-type MoS2. Phys. Status Solidi A 2024, 221, 2300913,  DOI: 10.1002/pssa.202300913
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    Schauble, K.; Zakhidov, D.; Yalon, E.; Deshmukh, S.; Grady, R. W.; Cooley, K. A.; McClellan, C. J.; Vaziri, S.; Passarello, D.; Mohney, S. E. Uncovering the Effects of Metal Contacts on Monolayer MoS2. ACS Nano 2020, 14 (11), 14798– 14808,  DOI: 10.1021/acsnano.0c03515
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    16
    Uncovering the Effects of Metal Contacts on Monolayer MoS2
    Schauble, Kirstin; Zakhidov, Dante; Yalon, Eilam; Deshmukh, Sanchit; Grady, Ryan W.; Cooley, Kayla A.; McClellan, Connor J.; Vaziri, Sam; Passarello, Donata; Mohney, Suzanne E.; Toney, Michael F.; Sood, A. K.; Salleo, Alberto; Pop, Eric
    ACS Nano (2020), 14 (11), 14798-14808CODEN: ANCAC3; ISSN:1936-0851. (American Chemical Society)
    Metal contacts are a key limiter to the electronic performance of two-dimensional (2D) semiconductor devices. Here, we present a comprehensive study of contact interfaces between seven metals (Y, Sc, Ag, Al, Ti, Au, Ni, with work functions from 3.1 to 5.2 eV) and monolayer MoS2 grown by chem. vapor deposition. We evap. thin metal films onto MoS2 and study the interfaces by Raman spectroscopy, XPS, X-ray diffraction, transmission electron microscopy, and elec. characterization. We uncover that (1) ultrathin oxidized Al dopes MoS2n-type (>2 x 1012 cm-2) without degrading its mobility, (2) Ag, Au, and Ni deposition causes varying levels of damage to MoS2 (e.g. broadening Raman E' peak from <3 to >6 cm-1), and (3) Ti, Sc, and Y react with MoS2. Reactive metals must be avoided in contacts to monolayer MoS2, but control studies reveal the reaction is mostly limited to the top layer of multilayer films. Finally, we find that (4) thin metals do not significantly strain MoS2, as confirmed by X-ray diffraction. These are important findings for metal contacts to MoS2 and broadly applicable to many other 2D semiconductors.
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  17. 17
    Yu, Y.; Yu, Y.; Xu, C.; Cai, Y.; Su, L.; Zhang, Y.; Zhang, Y.; Gundogdu, K.; Cao, L. Engineering Substrate Interactions for High Luminescence Efficiency of Transition-metal Dichalcogenide Monolayers. Adv. Funct. Mater. 2016, 26 (26), 4733– 4739,  DOI: 10.1002/adfm.201600418
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    17
    Engineering Substrate Interactions for High Luminescence Efficiency of Transition-Metal Dichalcogenide Monolayers
    Yu, Yifei; Yu, Yiling; Xu, Chao; Cai, Yong-Qing; Su, Liqin; Zhang, Yong; Zhang, Yong-Wei; Gundogdu, Kenan; Cao, Linyou
    Advanced Functional Materials (2016), 26 (26), 4733-4739CODEN: AFMDC6; ISSN:1616-301X. (Wiley-VCH Verlag GmbH & Co. KGaA)
    It is demonstrated that the luminescence efficiency of monolayers composed of MoS2, WS2, and WSe2 is significantly limited by the substrate and can be improved by orders of magnitude through substrate engineering. The substrate affects the efficiency mainly through doping the monolayers and facilitating defect-assisted nonradiative exciton recombinations, while the other substrate effects including straining and dielec. screening play minor roles. The doping may come from the substrate and substrate-borne water moisture, the latter of which is much stronger than the former for MoS2 and WS2 but negligible for WSe2. Using proper substrates such as mica or hexagonal boron nitride can substantially mitigate the doping effect. The defect-assisted recombination depends on the interaction between the defect in the monolayer and the substrate. Suspended monolayers, in which the substrate effects are eliminated, may have efficiency up to 40% at room temps. The result provides useful guidance for the rational design of at.-scale light emission devices.
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  18. 18
    Oberoi, A.; Han, Y.; Stepanoff, S. P.; Pannone, A.; Sun, Y.; Lin, Y.-C.; Chen, C.; Shallenberger, J. R.; Zhou, D.; Terrones, M. Toward High-Performance P-Type Two-Dimensional Field Effect Transistors: Contact Engineering, Scaling, and Doping. ACS Nano 2023, 17 (20), 19709– 19723,  DOI: 10.1021/acsnano.3c03060
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    18
    Toward High-Performance p-Type Two-Dimensional Field Effect Transistors: Contact Engineering, Scaling, and Doping
    Oberoi, Aaryan; Han, Ying; Stepanoff, Sergei P.; Pannone, Andrew; Sun, Yongwen; Lin, Yu-Chuan; Chen, Chen; Shallenberger, Jeffrey R.; Zhou, Da; Terrones, Mauricio; Redwing, Joan M.; Robinson, Joshua A.; Wolfe, Douglas E.; Yang, Yang; Das, Saptarshi
    ACS Nano (2023), 17 (20), 19709-19723CODEN: ANCAC3; ISSN:1936-0851. (American Chemical Society)
    N-type field effect transistors (FETs) based on two-dimensional (2D) transition-metal dichalcogenides (TMDs) such as MoS2 and WS2 have come close to meeting the requirements set forth in the International Roadmap for Devices and Systems (IRDS). However, p-type 2D FETs are dramatically lagging behind in meeting performance stds. Here, we adopt a three-pronged approach that includes contact engineering, channel length (Lch) scaling, and monolayer doping to achieve high performance p-type FETs based on synthetic WSe2. Using elec. measurements backed by atomistic imaging and rigorous anal., Pd was identified as the favorable contact metal for WSe2 owing to better epitaxy, larger grain size, and higher compressive strain, leading to a lower Schottky barrier height. While the ON-state performance of Pd-contacted WSe2 FETs was improved by ~ 10x by aggressively scaling Lch from 1μm down to ~ 20 nm, ultrascaled FETs were found to be contact limited. To reduce the contact resistance, monolayer tungsten oxyselenide (WOxSey) obtained using self-limiting oxidn. of bilayer WSe2 was used as a p-type dopant. This led to ~ 5x improvement in the ON-state performance and ~ 9x redn. in the contact resistance. We were able to achieve a median ON-state current as high as ~ 10μA/μm for ultrascaled and doped p-type WSe2 FETs with Pd contacts. We also show the applicability of our monolayer doping strategy to other 2D materials such as MoS2, MoTe2, and MoSe2.
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  19. 19
    Pendurthi, R.; Sakib, N. U.; Sadaf, M. U. K.; Zhang, Z.; Sun, Y.; Chen, C.; Jayachandran, D.; Oberoi, A.; Ghosh, S.; Kumari, S. Monolithic Three-Dimensional Integration of Complementary Two-Dimensional Field-Effect Transistors. Nat. Nanotechnol. 2024, 19, 970– 977,  DOI: 10.1038/s41565-024-01705-2
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    Pu, J.; Funahashi, K.; Chen, C.-H.; Li, M.-Y.; Li, L.-J.; Takenobu, T. Highly Flexible and High-Performance Complementary Inverters of Large-Area Transition Metal Dichalcogenide Monolayers. Adv. Mater. 2016, 28 (21), 4111– 4119,  DOI: 10.1002/adma.201503872
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    20
    Highly-flexible and high-performance complementary inverters of large-area transition metal dichalcogenide monolayers
    Pu, Jiang; Funahashi, Kazuma; Chen, Chang-Hsiao; Li, Ming-Yang; Li, Lain-Jong; Takenobu, Taishi
    Advanced Materials (Weinheim, Germany) (2016), 28 (21), 4111-4119CODEN: ADVMEW; ISSN:0935-9648. (Wiley-VCH Verlag GmbH & Co. KGaA)
    We demonstrate CMOS inverters using large-area transition metal dichalcogenide (TMDC) monolayers grown with CVD methods. Gelated ionic liqs. are adopted as a gate electrolyte. By combining p-type WSe2 and n-type MoS2 elec. double layer transistors (EDLTs), we demonstrate CMOS inverters with the highest voltage gain among 2D materials, with negligible off-state voltage, large total noise margin, low power consumption, and good switching speed. Moreover, we transfer these inverters onto plastic substrates and evaluate their bendability. The inverters on flexible substrates exhibit stable operation, even when the devices are bent to a curvature radius of 0.5 mm, thus demonstrating highly flexible CMOS inverters of large-area TMDCs.
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    Piacentini, A.; Polyushkin, D.; Uzlu, B.; Grundmann, A.; Heuken, M.; Kalisch, H.; Vescan, A.; Mueller, T.; Lemme, M. C.; Neumaier, D. Flexible CMOS Electronics Based on 2D P-Type WSe2 and n-Type MoS2. In 2023 Device Research Conference (DRC); IEEE: 2023; pp 1– 2.
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    Shih, P.-S.; Zan, H.-W.; Chang, T.-C.; Huang, T.-Y.; Chang, C.-Y. Dimensional Effects on the Drain Current of N-and P-Channel Polycrystalline Silicon Thin Film Transistors. Jpn. J. Appl. Phys. 2000, 39 (7R), 3879,  DOI: 10.1143/JJAP.39.3879
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    Wang, A. W.; Saraswat, K. C. Modeling of Grain Size Variation Effects in Polycrystalline Thin Film Transistors. In International Electron Devices Meeting 1998. Technical Digest (Cat. No. 98CH36217); IEEE: 1998; pp 277– 280.
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    Yamauchi, N.; Hajjar, J.-J.; Reif, R. Polysilicon Thin-Film Transistors with Channel Length and Width Comparable to or Smaller than the Grain Size of the Thin Film. IEEE Trans. Electron Devices 1991, 38 (1), 55– 60,  DOI: 10.1109/16.65736
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    Daus, A.; Vogt, C.; Münzenrieder, N.; Petti, L.; Knobelspies, S.; Cantarella, G.; Luisier, M.; Salvatore, G. A.; Tröster, G. Charge Trapping Mechanism Leading to Sub-60-MV/Decade-Swing FETs. IEEE Trans. Electron Devices 2017, 64 (7), 2789– 2796,  DOI: 10.1109/TED.2017.2703914
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    25
    Charge trapping mechanism leading to sub-60-mV/decade-swing FETs
    Daus, Alwin; Vogt, Christian; Muenzenrieder, Niko; Petti, Luisa; Knobelspies, Stefan; Cantarella, Giuseppe; Luisier, Mathieu; Salvatore, Giovanni A.; Troester, Gerhard
    IEEE Transactions on Electron Devices (2017), 64 (7), 2789-2796CODEN: IETDAI; ISSN:1557-9646. (Institute of Electrical and Electronics Engineers)
    In this paper, we present a novel method to reduce the subthreshold swing (SS) of FETs below 60 mV/decade. Through modeling, we directly relate trap charge movement between the gate electrode and the gate dielec. to SS redn. We exptl. investigate the impact of charge exchange between a Cu gate electrode and a 5-nm-thick amorphous Al2O3 gate dielec. in an InGaZnO4 thin-film transistor. Pos. trap charges are generated inside the gate dielec. while the semiconductor is in accumulation. During the subsequent detrapping, the SS diminishes to a min. value of 46 mV/decade at room temp. Furthermore, we relate the charge trapping/detrapping effects to a neg. capacitance behavior of the Cu/Al2O3 metal-insulator structure.
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  26. 26
    Daus, A.; Hoang, L.; Gilardi, C.; Wahid, S.; Kwon, J.; Qin, S.; Ko, J.-S.; Islam, M.; Kumar, A.; Neilson, K. M. Effect of Back-Gate Dielectric on Indium Tin Oxide (ITO) Transistor Performance and Stability. IEEE Trans. Electron Devices 2023, 70, 5685– 5689,  DOI: 10.1109/TED.2023.3319300
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    Bolat, S.; Torres Sevilla, G.; Mancinelli, A.; Gilshtein, E.; Sastre, J.; Cabas Vidani, A.; Bachmann, D.; Shorubalko, I.; Briand, D.; Tiwari, A. N.; Romanyuk, Y. E. Synaptic Transistors with Aluminum Oxide Dielectrics Enabling Full Audio Frequency Range Signal Processing. Sci. Rep. 2020, 10 (1), 16664,  DOI: 10.1038/s41598-020-73705-w
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    Balakrishna Pillai, P.; De Souza, M. M. Nanoionics-Based Three-Terminal Synaptic Device Using Zinc Oxide. ACS Appl. Mater. Interfaces. 2017, 9 (2), 1609– 1618,  DOI: 10.1021/acsami.6b13746
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    28
    Nanoionics-Based Three-Terminal Synaptic Device Using Zinc Oxide
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    ACS Applied Materials & Interfaces (2017), 9 (2), 1609-1618CODEN: AAMICK; ISSN:1944-8244. (American Chemical Society)
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  • Abstract

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    Figure 1

    Figure 1. Fabrication process of flexible WSe2 FETs. (a) Fabrication process flow of flexible top-gated WSe2 transistors. (b) Optical images of WSe2 film with contacts before transfer on sapphire and after transfer on PI. (c) Raman spectra of as-grown WSe2 on sapphire and after transfer on PI. (d) Atomic force microscopy image of the as-grown WSe2. (e) Optical image of the flexible PI substrate after fabrication.

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    Figure 2

    Figure 2. Flexible p-type WSe2 devices. (a) Schematic device cross section. (b) Optical image of flexible FETs. Unlabeled contacts correspond to source/drain to measure channels. (c, d) Transfer characteristics of devices showing the highest ID on/off ratio in (c) and highest drain current |ID| in (d), including the corresponding gate leakage currents |IG|. (e, f) Benchmarking of flexible p-type WSe2 FETs comparing maximum |ID|, ID on/off ratio, and L. This work’s data are for |ID| at VDS = −1 V, and the values from others are indicated (see also Table S1).

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    Figure 3

    Figure 3. Flexible TMD devices under bias stress (BS). (a) Transfer characteristics of WSe2 FET under −5 V gate BS as a function of cumulative stress time t. (b) |ID| at VGS = −5 V versus t of four WSe2 FETs. (c) Transfer characteristic of MoS2 FET under +5 V gate BS as a function of t. (d) |ID| at VGS = +5 V versus t of four MoS2 FETs.

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    Figure 4

    Figure 4. Pulsed measurements: (a) ID normalized by ID at a 500 μs pulse width. For the ID values at dc, VGS was applied for ∼180 ms for each voltage step (Table S2). However, the voltage vs time profiles are different for both methods (Figure S7). (b) ΔVT of five WSe2 FETs versus pulse width. (c) Band diagram showing the charge trapping from gate to dielectric and from channel to dielectric. The blue and red defect bands in Al2O3 represent dominant trapping sites for electrons and holes, respectively. (34) We note that more defect energy levels might be available for trapping across different energies, which depends also on the dielectric deposition process. (35) (d) Hysteresis ΔVGS for one WSe2 FET measured with different pulse widths.

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  • References

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      Using elec. characteristics from three-terminal field-effect transistors (FETs), the authors demonstrate substantial strain induced band gap tunability in transition metal dichalcogenides (TMDs) in line with theor. predictions and optical expts. Devices were fabricated on flexible substrates, and a cantilever sample holder was used to apply uniaxial tensile strain to the various multilayer TMD FETs. Analyzing in particular transfer characteristics, it is argued that the modified device characteristics under strain are clear evidence of a band gap redn. of 100 meV in WSe2 under 1.35% uniaxial tensile strain at room temp. The obtained device characteristics imply that the band gap does not shrink uniformly under strain relative to a ref. potential defined by the source/drain contacts. Instead, the band gap change is only related to a change of the conduction band edge of WSe2, resulting in a decrease in the Schottky barrier (SB) for electrons without any change for hole injection into the valence band. Simulations of SB device characteristics are employed to explain this point and to quantify our findings. Last, our exptl. results are compared with DFT calcns. under strain showing excellent agreement between theor. predictions and the exptl. data presented here.
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    11. 11
      Zou, Y.; Zhang, Z.; Yan, J.; Lin, L.; Huang, G.; Tan, Y.; You, Z.; Li, P. High-Temperature Flexible WSe2 Photodetectors with Ultrahigh Photoresponsivity. Nat. Commun. 2022, 13 (1), 4372,  DOI: 10.1038/s41467-022-32062-0
      11
      High-temperature flexible WSe2 photodetectors with ultrahigh photoresponsivity
      Zou, Yixuan; Zhang, Zekun; Yan, Jiawen; Lin, Linhan; Huang, Guanyao; Tan, Yidong; You, Zheng; Li, Peng
      Nature Communications (2022), 13 (1), 4372CODEN: NCAOBW; ISSN:2041-1723. (Nature Portfolio)
      The development of high-temp. photodetectors can be beneficial for numerous applications, such as aerospace engineering, military defense and harsh-environments robotics. However, current high-temp. photodetectors are characterized by low photoresponsivity (<10 A/W) due to the poor optical sensitivity of commonly used heat-resistant materials. Here, we report the realization of h-BN-encapsulated graphite/WSe2 photodetectors which can endure temps. up to 700°C in air (1000°C in vacuum) and exhibit unconventional neg. photocond. (NPC) at high temps. Operated in NPC mode, the devices show a photoresponsivity up to 2.2 x 106 A/W, which is ∼5 orders of magnitude higher than that of state-of-the-art high-temp. photodetectors. Furthermore, our devices demonstrate good flexibility, making it highly adaptive to various shaped surfaces. Our approach can be extended to other 2D materials and may stimulate further developments of 2D optoelectronic devices operating in harsh environments.
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    12. 12
      Ming, Z.; Sun, H.; Wang, H.; Sheng, Z.; Wang, Y.; Zhang, Z. Full Two-Dimensional Ambipolar Field-Effect Transistors for Transparent and Flexible Electronics. ACS Appl. Mater. Interfaces 2024, 16, 45131– 45138,  DOI: 10.1021/acsami.4c06602
      There is no corresponding record for this reference.
    13. 13
      Grundmann, A.; Beckmann, Y.; Ghiami, A.; Bui, M.; Kardynal, B.; Patterer, L.; Schneider, J.; Kummell, T.; Bacher, G.; Heuken, M.; Kalisch, H.; Vescan, A. Impact of Synthesis Temperature and Precursor Ratio on the Crystal Quality of MOCVD WSe2 Monolayers. Nanotechnology 2023, 34 (20), 205602,  DOI: 10.1088/1361-6528/acb947
      There is no corresponding record for this reference.
    14. 14
      Nassiri Nazif, K.; Daus, A.; Hong, J.; Lee, N.; Vaziri, S.; Kumar, A.; Nitta, F.; Chen, M. E.; Kananian, S.; Islam, R. High-Specific-Power Flexible Transition Metal Dichalcogenide Solar Cells. Nat. Commun. 2021, 12 (1), 7034,  DOI: 10.1038/s41467-021-27195-7
      14
      High-specific-power flexible transition metal dichalcogenide solar cells
      Nassiri Nazif, Koosha; Daus, Alwin; Hong, Jiho; Lee, Nayeun; Vaziri, Sam; Kumar, Aravindh; Nitta, Frederick; Chen, Michelle E.; Kananian, Siavash; Islam, Raisul; Kim, Kwan-Ho; Park, Jin-Hong; Poon, Ada S. Y.; Brongersma, Mark L.; Pop, Eric; Saraswat, Krishna C.
      Nature Communications (2021), 12 (1), 7034CODEN: NCAOBW; ISSN:2041-1723. (Nature Research)
      Semiconducting transition metal dichalcogenides (TMDs) are promising for flexible high-specific-power photovoltaics due to their ultrahigh optical absorption coeffs., desirable band gaps and self-passivated surfaces. However, challenges such as Fermi-level pinning at the metal contact-TMD interface and the inapplicability of traditional doping schemes have prevented most TMD solar cells from exceeding 2% power conversion efficiency (PCE). In addn., fabrication on flexible substrates tends to contaminate or damage TMD interfaces, further reducing performance. Here, we address these fundamental issues by employing: (1) transparent graphene contacts to mitigate Fermi-level pinning, (2) MoOx capping for doping, passivation and anti-reflection, and (3) a clean, non-damaging direct transfer method to realize devices on lightwt. flexible polyimide substrates. These lead to record PCE of 5.1% and record specific power of 4.4 W g-1 for flexible TMD (WSe2) solar cells, the latter on par with prevailing thin-film solar technologies cadmium telluride, copper indium gallium selenide, amorphous silicon and III-Vs. We further project that TMD solar cells could achieve specific power up to 46 W g-1, creating unprecedented opportunities in a broad range of industries from aerospace to wearable and implantable electronics.
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    15. 15
      Piacentini, A.; Polyushkin, D. K.; Uzlu, B.; Grundmann, A.; Heuken, M.; Kalisch, H.; Vescan, A.; Wang, Z.; Lemme, M. C.; Mueller, T.; Neumaier, D. Flexible Complementary Metal-Oxide-Semiconductor Inverter Based on 2D P-type WSe2 and N-type MoS2. Phys. Status Solidi A 2024, 221, 2300913,  DOI: 10.1002/pssa.202300913
      There is no corresponding record for this reference.
    16. 16
      Schauble, K.; Zakhidov, D.; Yalon, E.; Deshmukh, S.; Grady, R. W.; Cooley, K. A.; McClellan, C. J.; Vaziri, S.; Passarello, D.; Mohney, S. E. Uncovering the Effects of Metal Contacts on Monolayer MoS2. ACS Nano 2020, 14 (11), 14798– 14808,  DOI: 10.1021/acsnano.0c03515
      16
      Uncovering the Effects of Metal Contacts on Monolayer MoS2
      Schauble, Kirstin; Zakhidov, Dante; Yalon, Eilam; Deshmukh, Sanchit; Grady, Ryan W.; Cooley, Kayla A.; McClellan, Connor J.; Vaziri, Sam; Passarello, Donata; Mohney, Suzanne E.; Toney, Michael F.; Sood, A. K.; Salleo, Alberto; Pop, Eric
      ACS Nano (2020), 14 (11), 14798-14808CODEN: ANCAC3; ISSN:1936-0851. (American Chemical Society)
      Metal contacts are a key limiter to the electronic performance of two-dimensional (2D) semiconductor devices. Here, we present a comprehensive study of contact interfaces between seven metals (Y, Sc, Ag, Al, Ti, Au, Ni, with work functions from 3.1 to 5.2 eV) and monolayer MoS2 grown by chem. vapor deposition. We evap. thin metal films onto MoS2 and study the interfaces by Raman spectroscopy, XPS, X-ray diffraction, transmission electron microscopy, and elec. characterization. We uncover that (1) ultrathin oxidized Al dopes MoS2n-type (>2 x 1012 cm-2) without degrading its mobility, (2) Ag, Au, and Ni deposition causes varying levels of damage to MoS2 (e.g. broadening Raman E' peak from <3 to >6 cm-1), and (3) Ti, Sc, and Y react with MoS2. Reactive metals must be avoided in contacts to monolayer MoS2, but control studies reveal the reaction is mostly limited to the top layer of multilayer films. Finally, we find that (4) thin metals do not significantly strain MoS2, as confirmed by X-ray diffraction. These are important findings for metal contacts to MoS2 and broadly applicable to many other 2D semiconductors.
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    17. 17
      Yu, Y.; Yu, Y.; Xu, C.; Cai, Y.; Su, L.; Zhang, Y.; Zhang, Y.; Gundogdu, K.; Cao, L. Engineering Substrate Interactions for High Luminescence Efficiency of Transition-metal Dichalcogenide Monolayers. Adv. Funct. Mater. 2016, 26 (26), 4733– 4739,  DOI: 10.1002/adfm.201600418
      17
      Engineering Substrate Interactions for High Luminescence Efficiency of Transition-Metal Dichalcogenide Monolayers
      Yu, Yifei; Yu, Yiling; Xu, Chao; Cai, Yong-Qing; Su, Liqin; Zhang, Yong; Zhang, Yong-Wei; Gundogdu, Kenan; Cao, Linyou
      Advanced Functional Materials (2016), 26 (26), 4733-4739CODEN: AFMDC6; ISSN:1616-301X. (Wiley-VCH Verlag GmbH & Co. KGaA)
      It is demonstrated that the luminescence efficiency of monolayers composed of MoS2, WS2, and WSe2 is significantly limited by the substrate and can be improved by orders of magnitude through substrate engineering. The substrate affects the efficiency mainly through doping the monolayers and facilitating defect-assisted nonradiative exciton recombinations, while the other substrate effects including straining and dielec. screening play minor roles. The doping may come from the substrate and substrate-borne water moisture, the latter of which is much stronger than the former for MoS2 and WS2 but negligible for WSe2. Using proper substrates such as mica or hexagonal boron nitride can substantially mitigate the doping effect. The defect-assisted recombination depends on the interaction between the defect in the monolayer and the substrate. Suspended monolayers, in which the substrate effects are eliminated, may have efficiency up to 40% at room temps. The result provides useful guidance for the rational design of at.-scale light emission devices.
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    18. 18
      Oberoi, A.; Han, Y.; Stepanoff, S. P.; Pannone, A.; Sun, Y.; Lin, Y.-C.; Chen, C.; Shallenberger, J. R.; Zhou, D.; Terrones, M. Toward High-Performance P-Type Two-Dimensional Field Effect Transistors: Contact Engineering, Scaling, and Doping. ACS Nano 2023, 17 (20), 19709– 19723,  DOI: 10.1021/acsnano.3c03060
      18
      Toward High-Performance p-Type Two-Dimensional Field Effect Transistors: Contact Engineering, Scaling, and Doping
      Oberoi, Aaryan; Han, Ying; Stepanoff, Sergei P.; Pannone, Andrew; Sun, Yongwen; Lin, Yu-Chuan; Chen, Chen; Shallenberger, Jeffrey R.; Zhou, Da; Terrones, Mauricio; Redwing, Joan M.; Robinson, Joshua A.; Wolfe, Douglas E.; Yang, Yang; Das, Saptarshi
      ACS Nano (2023), 17 (20), 19709-19723CODEN: ANCAC3; ISSN:1936-0851. (American Chemical Society)
      N-type field effect transistors (FETs) based on two-dimensional (2D) transition-metal dichalcogenides (TMDs) such as MoS2 and WS2 have come close to meeting the requirements set forth in the International Roadmap for Devices and Systems (IRDS). However, p-type 2D FETs are dramatically lagging behind in meeting performance stds. Here, we adopt a three-pronged approach that includes contact engineering, channel length (Lch) scaling, and monolayer doping to achieve high performance p-type FETs based on synthetic WSe2. Using elec. measurements backed by atomistic imaging and rigorous anal., Pd was identified as the favorable contact metal for WSe2 owing to better epitaxy, larger grain size, and higher compressive strain, leading to a lower Schottky barrier height. While the ON-state performance of Pd-contacted WSe2 FETs was improved by ~ 10x by aggressively scaling Lch from 1μm down to ~ 20 nm, ultrascaled FETs were found to be contact limited. To reduce the contact resistance, monolayer tungsten oxyselenide (WOxSey) obtained using self-limiting oxidn. of bilayer WSe2 was used as a p-type dopant. This led to ~ 5x improvement in the ON-state performance and ~ 9x redn. in the contact resistance. We were able to achieve a median ON-state current as high as ~ 10μA/μm for ultrascaled and doped p-type WSe2 FETs with Pd contacts. We also show the applicability of our monolayer doping strategy to other 2D materials such as MoS2, MoTe2, and MoSe2.
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    19. 19
      Pendurthi, R.; Sakib, N. U.; Sadaf, M. U. K.; Zhang, Z.; Sun, Y.; Chen, C.; Jayachandran, D.; Oberoi, A.; Ghosh, S.; Kumari, S. Monolithic Three-Dimensional Integration of Complementary Two-Dimensional Field-Effect Transistors. Nat. Nanotechnol. 2024, 19, 970– 977,  DOI: 10.1038/s41565-024-01705-2
      There is no corresponding record for this reference.
    20. 20
      Pu, J.; Funahashi, K.; Chen, C.-H.; Li, M.-Y.; Li, L.-J.; Takenobu, T. Highly Flexible and High-Performance Complementary Inverters of Large-Area Transition Metal Dichalcogenide Monolayers. Adv. Mater. 2016, 28 (21), 4111– 4119,  DOI: 10.1002/adma.201503872
      20
      Highly-flexible and high-performance complementary inverters of large-area transition metal dichalcogenide monolayers
      Pu, Jiang; Funahashi, Kazuma; Chen, Chang-Hsiao; Li, Ming-Yang; Li, Lain-Jong; Takenobu, Taishi
      Advanced Materials (Weinheim, Germany) (2016), 28 (21), 4111-4119CODEN: ADVMEW; ISSN:0935-9648. (Wiley-VCH Verlag GmbH & Co. KGaA)
      We demonstrate CMOS inverters using large-area transition metal dichalcogenide (TMDC) monolayers grown with CVD methods. Gelated ionic liqs. are adopted as a gate electrolyte. By combining p-type WSe2 and n-type MoS2 elec. double layer transistors (EDLTs), we demonstrate CMOS inverters with the highest voltage gain among 2D materials, with negligible off-state voltage, large total noise margin, low power consumption, and good switching speed. Moreover, we transfer these inverters onto plastic substrates and evaluate their bendability. The inverters on flexible substrates exhibit stable operation, even when the devices are bent to a curvature radius of 0.5 mm, thus demonstrating highly flexible CMOS inverters of large-area TMDCs.
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    21. 21
      Piacentini, A.; Polyushkin, D.; Uzlu, B.; Grundmann, A.; Heuken, M.; Kalisch, H.; Vescan, A.; Mueller, T.; Lemme, M. C.; Neumaier, D. Flexible CMOS Electronics Based on 2D P-Type WSe2 and n-Type MoS2. In 2023 Device Research Conference (DRC); IEEE: 2023; pp 1– 2.
      There is no corresponding record for this reference.
    22. 22
      Shih, P.-S.; Zan, H.-W.; Chang, T.-C.; Huang, T.-Y.; Chang, C.-Y. Dimensional Effects on the Drain Current of N-and P-Channel Polycrystalline Silicon Thin Film Transistors. Jpn. J. Appl. Phys. 2000, 39 (7R), 3879,  DOI: 10.1143/JJAP.39.3879
      There is no corresponding record for this reference.
    23. 23
      Wang, A. W.; Saraswat, K. C. Modeling of Grain Size Variation Effects in Polycrystalline Thin Film Transistors. In International Electron Devices Meeting 1998. Technical Digest (Cat. No. 98CH36217); IEEE: 1998; pp 277– 280.
      There is no corresponding record for this reference.
    24. 24
      Yamauchi, N.; Hajjar, J.-J.; Reif, R. Polysilicon Thin-Film Transistors with Channel Length and Width Comparable to or Smaller than the Grain Size of the Thin Film. IEEE Trans. Electron Devices 1991, 38 (1), 55– 60,  DOI: 10.1109/16.65736
      There is no corresponding record for this reference.
    25. 25
      Daus, A.; Vogt, C.; Münzenrieder, N.; Petti, L.; Knobelspies, S.; Cantarella, G.; Luisier, M.; Salvatore, G. A.; Tröster, G. Charge Trapping Mechanism Leading to Sub-60-MV/Decade-Swing FETs. IEEE Trans. Electron Devices 2017, 64 (7), 2789– 2796,  DOI: 10.1109/TED.2017.2703914
      25
      Charge trapping mechanism leading to sub-60-mV/decade-swing FETs
      Daus, Alwin; Vogt, Christian; Muenzenrieder, Niko; Petti, Luisa; Knobelspies, Stefan; Cantarella, Giuseppe; Luisier, Mathieu; Salvatore, Giovanni A.; Troester, Gerhard
      IEEE Transactions on Electron Devices (2017), 64 (7), 2789-2796CODEN: IETDAI; ISSN:1557-9646. (Institute of Electrical and Electronics Engineers)
      In this paper, we present a novel method to reduce the subthreshold swing (SS) of FETs below 60 mV/decade. Through modeling, we directly relate trap charge movement between the gate electrode and the gate dielec. to SS redn. We exptl. investigate the impact of charge exchange between a Cu gate electrode and a 5-nm-thick amorphous Al2O3 gate dielec. in an InGaZnO4 thin-film transistor. Pos. trap charges are generated inside the gate dielec. while the semiconductor is in accumulation. During the subsequent detrapping, the SS diminishes to a min. value of 46 mV/decade at room temp. Furthermore, we relate the charge trapping/detrapping effects to a neg. capacitance behavior of the Cu/Al2O3 metal-insulator structure.
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    26. 26
      Daus, A.; Hoang, L.; Gilardi, C.; Wahid, S.; Kwon, J.; Qin, S.; Ko, J.-S.; Islam, M.; Kumar, A.; Neilson, K. M. Effect of Back-Gate Dielectric on Indium Tin Oxide (ITO) Transistor Performance and Stability. IEEE Trans. Electron Devices 2023, 70, 5685– 5689,  DOI: 10.1109/TED.2023.3319300
      There is no corresponding record for this reference.
    27. 27
      Bolat, S.; Torres Sevilla, G.; Mancinelli, A.; Gilshtein, E.; Sastre, J.; Cabas Vidani, A.; Bachmann, D.; Shorubalko, I.; Briand, D.; Tiwari, A. N.; Romanyuk, Y. E. Synaptic Transistors with Aluminum Oxide Dielectrics Enabling Full Audio Frequency Range Signal Processing. Sci. Rep. 2020, 10 (1), 16664,  DOI: 10.1038/s41598-020-73705-w
      There is no corresponding record for this reference.
    28. 28
      Balakrishna Pillai, P.; De Souza, M. M. Nanoionics-Based Three-Terminal Synaptic Device Using Zinc Oxide. ACS Appl. Mater. Interfaces. 2017, 9 (2), 1609– 1618,  DOI: 10.1021/acsami.6b13746
      28
      Nanoionics-Based Three-Terminal Synaptic Device Using Zinc Oxide
      Balakrishna Pillai, Premlal; De Souza, Maria Merlyne
      ACS Applied Materials & Interfaces (2017), 9 (2), 1609-1618CODEN: AAMICK; ISSN:1944-8244. (American Chemical Society)
      Artificial synaptic Thin Film Transistors (TFTs) capable of simultaneously manifesting signal transmission and self-learning are demonstrated using transparent zinc oxide (ZnO) in combination with high κ tantalum oxide as gate insulator. The devices exhibit pronounced memory retention with a memory window >4V realized using an operating voltage <6V. Gate polarity induced motion of oxygen vacancies in the gate insulator is proposed to play a vital role in emulating synaptic behavior, directly measured as the transmission of a signal between the source and drain (S/D) terminals, but with the added benefit of independent control of synaptic wt. Unlike in two terminal memristor/resistive switching devices, multistate memory levels are demonstrated using the gate terminal without hampering the signal transmission across the S/D electrodes. Synaptic functions in the devices can be emulated using a low programming voltage of 200 mV, an order of magnitude smaller than in conventional resistive random access memory and other field effect transistor based synaptic technologies. Robust synaptic properties demonstrated using fully transparent, ecofriendly inorg. materials chosen here show greater promise in realizing scalable synaptic devices compared to org. synaptic and other liq. electrolyte gated device technologies. Most importantly, the strong coupling between the in-plane gate and semiconductor channel through ionic charge in the gate insulator shown by these devices, can lead to an artificial neural network with multiple pre-synaptic terminals for complex synaptic learning processes. This provides opportunities to alleviate the extreme requirements of component and interconnect d. in realizing brain-like systems.
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    29. 29
      Xu, W.; Dai, M.; Liang, L.; Liu, Z.; Sun, X.; Wan, Q.; Cao, H. Anomalous Bias-Stress-Induced Unstable Phenomena of InZnO Thin-Film Transistors Using Ta2O5 Gate Dielectric. J. Phys. D: Appl. Phys. 2012, 45 (20), 205103,  DOI: 10.1088/0022-3727/45/20/205103
      There is no corresponding record for this reference.
    30. 30
      Wager, J. F.; Keszler, D. A.; Presley, R. E. Transparent Electronics; Springer: 2008; Vol. 112.
      There is no corresponding record for this reference.
    31. 31
      Segantini, M.; Ballesio, A.; Palmara, G.; Zaccagnini, P.; Frascella, F.; Garzone, G.; Marasso, S. L.; Cocuzza, M.; Parmeggiani, M. Investigation and Modeling of the Electrical Bias Stress in Electrolyte-Gated Organic Transistors. Adv. Electron. Mater. 2022, 8 (7), 2101332,  DOI: 10.1002/aelm.202101332
      There is no corresponding record for this reference.
    32. 32
      Sinno, H.; Fabiano, S.; Crispin, X.; Berggren, M.; Engquist, I. Bias Stress Effect in Polyelectrolyte-Gated Organic Field-Effect Transistors. Appl. Phys. Lett. 2013, 102 (11), 113306,  DOI: 10.1063/1.4798512
      There is no corresponding record for this reference.
    33. 33
      Knobloch, T.; Uzlu, B.; Illarionov, Y. Y.; Wang, Z.; Otto, M.; Filipovic, L.; Waltl, M.; Neumaier, D.; Lemme, M. C.; Grasser, T. Improving Stability in Two-Dimensional Transistors with Amorphous Gate Oxides by Fermi-Level Tuning. Nat. Electron. 2022, 5 (6), 356– 366,  DOI: 10.1038/s41928-022-00768-0
      There is no corresponding record for this reference.
    34. 34
      Knobloch, T.; Waldhoer, D.; Davoudi, M. R.; Karl, A.; Khakbaz, P.; Matzinger, M.; Zhang, Y.; Smithe, K. K. H.; Nazir, A.; Liu, C. Modeling the Performance and Reliability of Two-Dimensional Semiconductor Transistors. In 2023 International Electron Devices Meeting (IEDM); IEEE: 2023; pp 1– 4.
      There is no corresponding record for this reference.
    35. 35
      Degraeve, R.; Cho, M.; Govoreanu, B.; Kaczer, B.; Zahid, M. B.; Van Houdt, J.; Jurczak, M.; Groeseneken, G. Trap Spectroscopy by Charge Injection and Sensing (TSCIS): A Quantitative Electrical Technique for Studying Defects in Dielectric Stacks. In 2008 IEEE International Electron Devices Meeting; IEEE: 2008; pp 1– 4.
      There is no corresponding record for this reference.
    36. 36
      Daus, A.; Vogt, C.; Münzenrieder, N.; Petti, L.; Knobelspies, S.; Cantarella, G.; Luisier, M.; Salvatore, G. A.; Tröster, G. Positive Charge Trapping Phenomenon in N-Channel Thin-Film Transistors with Amorphous Alumina Gate Insulators. J. Appl. Phys. 2016, 120 (24), 244501,  DOI: 10.1063/1.4972475
      37
      Positive charge trapping phenomenon in n-channel thin-film transistors with amorphous alumina gate insulators
      Daus, Alwin; Vogt, Christian; Munzenrieder, Niko; Petti, Luisa; Knobelspies, Stefan; Cantarella, Giuseppe; Luisier, Mathieu; Salvatore, Giovanni A.; Troster, Gerhard
      Journal of Applied Physics (Melville, NY, United States) (2016), 120 (24), 244501/1-244501/6CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)
      In this work, we investigate the charge trapping behavior in InGaZnO4 (IGZO) thin-film transistors with amorphous Al2O3 (alumina) gate insulators. For thicknesses ≤10 nm, we observe a pos. charge generation at intrinsic defects inside the Al2O3, which is initiated by quantum-mech. tunneling of electrons from the semiconductor through the Al2O3 layer. Consequently, the drain current shows a counter-clockwise hysteresis. Furthermore, the de-trapping through resonant tunneling causes a drastic subthreshold swing redn. We report a min. value of 19 mV/dec at room temp., which is far below the fundamental limit of std. field-effect transistors. Addnl., we study the thickness dependence for Al2O3 layers with thicknesses of 5, 10, and 20 nm. The comparison of two different gate metals shows an enhanced tunneling current and an enhanced pos. charge generation for Cu compared to Cr. (c) 2016 American Institute of Physics.
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    37. 37
      Zeumault, A.; Subramanian, V. Mobility Enhancement in Solution-Processed Transparent Conductive Oxide TFTs Due to Electron Donation from Traps in High-k Gate Dielectrics. Adv. Funct. Mater. 2016, 26 (6), 955– 963,  DOI: 10.1002/adfm.201503940
      There is no corresponding record for this reference.
    38. 38
      Datye, I. M.; Gabourie, A. J.; English, C. D.; Smithe, K. K. H.; McClellan, C. J.; Wang, N. C.; Pop, E. Reduction of Hysteresis in MoS2 Transistors Using Pulsed Voltage Measurements. 2D Mater. 2019, 6 (1), 011004,  DOI: 10.1088/2053-1583/aae6a1
      39
      Reduction of hysteresis in MoS2 transistors using pulsed voltage measurements
      Datye, Isha M.; Gabourie, Alexander J.; English, Chris D.; Smithe, Kirby K. H.; McClellan, Connor J.; Wang, Ning C.; Pop, Eric
      2D Materials (2019), 6 (1), 011004CODEN: DMATB7; ISSN:2053-1583. (IOP Publishing Ltd.)
      Transistors based on two-dimensional (2D) materials often exhibit hysteresis in their elec. measurements, i.e. a dependence of measured current on voltage sweep direction due to charge trapping. Here we demonstrate a simple pulsed measurement technique which reduces this hysteretic behavior, enabling more accurate characterization of 2D transistors. We compare hysteresis and charge trapping in four types of devices fabricated from both exfoliated and synthetic MoS2, with SiO2 and HfO2 insulators, using DC and pulsed voltage measurements at different temps. Applying modest voltage pulses (∼1 ms) on the gate significantly reduces charge trapping and results in the elimination of over 80% of hysteresis for all devices. At shorter pulse widths (∼1μs), up to 99% of hysteresis is reduced for some devices. Our measurements enable the extn. of a unique value of field-effect mobility, regardless of voltage sweep direction, unlike measurements that rely on forward or backward DC measurements. This simple and reproducible technique is useful for studying the intrinsic properties of 2D transistors, and can be similarly applied to other nanoscale and emerging devices where charge trapping is of concern.
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    39. 39
      Illarionov, Y. Y.; Karl, A.; Smets, Q.; Kaczer, B.; Knobloch, T.; Panarella, L.; Schram, T.; Brems, S.; Cott, D.; Asselberghs, I. Process Implications on the Stability and Reliability of 300 mm FAB MoS2 Field-Effect Transistors. npj 2D Mater. Appl. 2024, 8 (1), 8,  DOI: 10.1038/s41699-024-00445-0
      There is no corresponding record for this reference.
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      Fleetwood, D. M. “Border Traps” in MOS Devices. IEEE Trans. Nucl. Sci. 1992, 39 (2), 269– 271,  DOI: 10.1109/23.277495
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    41. 41
      Illarionov, Y. Y.; Knobloch, T.; Jech, M.; Lanza, M.; Akinwande, D.; Vexler, M. I.; Mueller, T.; Lemme, M. C.; Fiori, G.; Schwierz, F.; Grasser, T. Insulators for 2D Nanoelectronics: The Gap to Bridge. Nat. Commun. 2020, 11 (1), 3385,  DOI: 10.1038/s41467-020-16640-8
      42
      Insulators for 2D nanoelectronics: the gap to bridge
      Illarionov, Yury Yu.; Knobloch, Theresia; Jech, Markus; Lanza, Mario; Akinwande, Deji; Vexler, Mikhail I.; Mueller, Thomas; Lemme, Max C.; Fiori, Gianluca; Schwierz, Frank; Grasser, Tibor
      Nature Communications (2020), 11 (1), 3385CODEN: NCAOBW; ISSN:2041-1723. (Nature Research)
      A review. Abstr.: Nanoelectronic devices based on 2D materials are far from delivering their full theor. performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technol. have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielec. specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mind set with respect to suitable insulators for 2D technologies may be required. We review possible soln. scenarios like the creation of clean interfaces, prodn. of native oxides from 2D semiconductors and more intensive studies on cryst. insulators.
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  • Supporting Information

    Supporting Information

    The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsami.4c13296.

    • Device fabrication, mobility extraction, additional data from bias stress and pulse measurements including hysteresis; additional SEM and AFM images and benchmarking information, device parameter statistics, capacitance measurements, data on device recovery after bias stress, additional information on measurement schemes for dc and pulsing; band diagram including references (PDF)


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