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Download Hi-Res ImageDownload to MS-PowerPointCite This:Nano Lett. 2012, 12, 2, 758-762
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Sub-10 nm Carbon Nanotube Transistor

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† IBM T. J. Watson Research Center, Yorktown Heights, New York 10598, United States
‡ Integrated Systems Laboratory, ETH Zurich, 8092 Zurich, Switzerland
§ School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907, United States
*E-mail: [email protected]
Cite this: Nano Lett. 2012, 12, 2, 758–762
Publication Date (Web):January 18, 2012
https://doi.org/10.1021/nl203701g
Copyright © 2012 American Chemical Society
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Abstract

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Although carbon nanotube (CNT) transistors have been promoted for years as a replacement for silicon technology, there is limited theoretical work and no experimental reports on how nanotubes will perform at sub-10 nm channel lengths. In this manuscript, we demonstrate the first sub-10 nm CNT transistor, which is shown to outperform the best competing silicon devices with more than four times the diameter-normalized current density (2.41 mA/μm) at a low operating voltage of 0.5 V. The nanotube transistor exhibits an impressively small inverse subthreshold slope of 94 mV/decade—nearly half of the value expected from a previous theoretical study. Numerical simulations show the critical role of the metal–CNT contacts in determining the performance of sub-10 nm channel length transistors, signifying the need for more accurate theoretical modeling of transport between the metal and nanotube. The superior low-voltage performance of the sub-10 nm CNT transistor proves the viability of nanotubes for consideration in future aggressively scaled transistor technologies.

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Detailed information on the transistor fabrication process, extraction of contact resistance, information on gate hysteresis and leakage current, output characteristics for different scaled channel lengths, and details on the numerical simulation with gate modulation of contacts. This material is available free of charge via the Internet at http://pubs.acs.org.

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