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Demonstration of Anti-ambipolar Switch and Its Applications for Extremely Low Power Ternary Logic Circuits
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  • Yongsu Lee
    Yongsu Lee
    Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
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  • Sunmean Kim
    Sunmean Kim
    Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
    More by Sunmean Kim
  • Ho-In Lee
    Ho-In Lee
    Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
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  • Seung-Mo Kim
    Seung-Mo Kim
    Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
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  • So-Young Kim
    So-Young Kim
    Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
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  • Kiyung Kim
    Kiyung Kim
    Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
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  • Heejin Kwon
    Heejin Kwon
    Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
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  • Hae-Won Lee
    Hae-Won Lee
    Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
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  • Hyeon Jun Hwang
    Hyeon Jun Hwang
    Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
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  • Seokhyeong Kang*
    Seokhyeong Kang
    Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
    *E-mail: [email protected]
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  • Byoung Hun Lee*
    Byoung Hun Lee
    Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
    *E-mail: [email protected]
    More by Byoung Hun Lee
    Orcidhttps://orcid.org/0000-0002-4540-7731
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ACS Nano

Cite this: ACS Nano 2022, 16, 7, 10994–11003
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https://doi.org/10.1021/acsnano.2c03523
Published June 28, 2022

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Abstract

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Anti-ambipolar switch (AAS) devices at a narrow bias region are necessary to solve the intrinsic leakage current problem of ternary logic circuits. In this study, an AAS device with a very high peak-to-valley ratio (∼106) and adjustable operating range characteristics was successfully demonstrated using a ZnO and dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene heterojunction structure. The entire device integration was completed at a low thermal budget of less than 200 °C, which makes this AAS device compatible with monolithic 3D integration. A 1-trit ternary full adder designed with this AAS device exhibits excellent power–delay product performance (∼122 aJ) with extremely low power (∼0.15 μW, 7 times lower than the reference circuit) and lower device count than those of other ternary device candidates.

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An increase in computing capabilities and integration density of CMOS devices has been achieved by reducing the minimum feature size of transistors. (1−5) However, as the power consumption at the interconnect region now accounts for more than 90% of active power consumption for highly scaled chips, a progressive improvement in transistor structure alone cannot be a proper solution for the significantly increasing power consumption. (3,4,6−9) Therefore, a more aggressive change in the chip architecture is necessary to deal with the power crisis for future data processing and other computing needs.
Multivalued logic (MVL) technology has been investigated as an alternative technology to overcome the significant rise in power consumption. (10−14) MVL is a computing architecture operating with more than two logic states. Therefore, MVL provides significant benefits in terms of the number of transistors and interconnection length required to accomplish identical functions compared to binary logic. Especially, ternary logic, which consists of three logic states (0, 1, and 2 or −1, 0, and +1), is the most extensively studied among the MVL architectures because it theoretically provides the lowest power consumption and best noise margin. (15−20)
The major bottleneck in ternary logic is the absence of a unit ternary device that can be integrated with the semiconductor process and operated in the same manner as MOSFETs, e.g., room-temperature operation and high drive current. Thus, early studies on ternary architecture were performed using a combination of binary devices. The carbon nanotube field-effect transistor (CNTFET) has been widely used for ternary circuit research owing to its high mobility, tunable threshold voltage (Vth), and very small physical dimensions. However, because of the difficulty in arranging multiple types of CNTs in an integrated circuit, studies on CNTFETs have only been performed theoretically. (17−19) The graphene barristor, the Schottky barrier triode between graphene and a semiconductor, was also suggested as a unit transistor for ternary circuits by Heo etal. because of the easy integration process and tunability of Vth to control the Schottky barrier height. (21)
In addition to the combination of binary devices, ternary circuit implementation using a unit ternary device has been reported. For quantum dot gate FETs, (20) an intermediate state was obtained by dynamic Vth shift owing to the tunneling charges accumulated in the quantum dot gate through a thin gate dielectric. However, it was difficult to fabricate two layers of well-aligned quantum dots, and the size limitation of quantum dots and the space between them restricted further scaling.
Recently, ternary devices with a dual-channel structure using graphene barristors have been suggested. The dual-channel ternary device utilizes two parallel channels with different Vth to obtain stepwise transfer characteristics. Kim etal. and Lee etal. demonstrated n-type and p-type dual-channel ternary devices with ZnO and dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT), respectively, and complementary ternary circuits were demonstrated. (22,23) Furthermore, ternary transistors with a stack-channel structure having two stacked ultrathin semiconductor channel layers with different Vth have been demonstrated. (24,25) In this device, the intermediate state was realized using an ultrathin phase composite ZnO layer having a voltage-independent constant current flow mechanism, which is attributed to the finite density of states in the conduction band from the mobility edge quantization phenomenon. Low process temperature and easy fabrication process make this device compatible with monolithic 3D integration.
A major challenge in ternary circuit design is finding a proper method to handle the intermediate state. When both devices in the ternary inverter are simultaneously in the intermediate state, a leakage current path between VDD and VGND is formed, leading to intrinsic power dissipation. (17−25) This leakage current mitigates the benefits of ternary logic, which is primarily associated with lower device count and less power consumption.
To avoid this problem, a ternary circuit scheme, called single pole triple throw (SPTT), has been proposed. (26) It uses an additional power rail for VDD/2. Although it becomes much more straightforward to obtain three states with this approach, the number of devices to form three states inevitably increases. Usually, two binary switches represent states 0 and 2, and two additional devices are necessary to represent state 1. The addition of power rails was technologically challenging in the 1970s; however, the recent progress in buried power rail technology can alleviate the area burden of additional power rails and contacts. (27,28) Thus, the SPTT approach became a promising technology for ternary architecture.
A single anti-ambipolar switch (AAS) device can replace the two devices required to emulate the intermediate state of a standard ternary inverter (STI) designed with an SPTT scheme. AAS devices pass information at a sharply limited gate bias range corresponding to the intermediate state, VDD/2. Thus, an appropriately designed AAS device can be used as a unit device in a pull-middle (PM) network, which is connected with a VDD/2 power rail. Peak-to-valley ratio (PVR), defined as the ratio of on (peak) current and off (valley) current, is one of the important characteristics of AAS devices. To implement the proposed ternary circuit, a high PVR is desirable because a high on current makes state transition fast, and a low off current reduces the power consumption due to the leakage current between networks, similar to the circuits using unipolar devices.
Several prior studies on AAS behavior used bias-dependent modulation of transconductance (gm) curves in Si, Ge, and III–V semiconductor devices. (29−35) Unfortunately, the low PVR in these devices limited their practical applications. Recently, various heterojunction devices using transition metal dichalcogenides (TMDCs), such as MoS2, WSe2, SnSeS, and ReS2, were proposed, and high current density and moderate PVR have been reported. (36−40) However, the difficulty of large-area integration of TMDC heterojunction devices and their compatibility with CMOS circuits are still a hurdle for practical applications. Thus, manufacturing an AAS device compatible with large-scale CMOS integration and having a reasonable performance at room temperature is one of the most important challenges in ternary logic technology.
Here, we report a ZnO–DNTT AAS device, with a high PVR of above 106, adjustable operation bias range, solid stability and reliability, and CMOS process compatibility, especially with back-on-the-line or 3D integrated circuits. The performance of the ternary full adder designed with the ZnO–DNTT AAS device exhibited ∼7 times lower power–delay product (PDP) than the ideal CNTFET-based ternary circuits in testing.

Results and Discussion

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Figure 1(a) shows the schematic device structure of the ZnO–DNTT AAS device. Bulk p++ Si substrate and 90 nm SiO2 are used as back gate and gate dielectric, respectively. On top of the gate dielectric, ZnO and DNTT channels are formed in sequence. Both semiconductors were selected because of the low process temperature required for monolithic 3D integration and air-stable characteristics required for device integration. ZnO was stably deposited using a low-temperature ALD process at 120 °C. (41,42) DNTT, a p-type organic thin-film semiconductor, was also deposited at room temperature using thermal evaporation. Both ZnO and DNTT showed reasonable air stability. The heterojunctions of the ZnO and DNTT layers partially overlap with each other, and Au electrodes contact each side of the heterojunction channels. The fabrication process is detailed in the Methods section (and Supporting Information, Figure S1). Figure 1(b) shows the fabricated device, with device dimensions of W = 180 μm and L = 420 μm for the overlapped regions and L = 300 μm for the underlapped regions. Figure 1(c) shows the cross-sectional TEM image of the ZnO–DNTT heterojunction. The XPS analysis of the ZnO channel indicates that ZnO is a bundle of nanorods having a wurtzite structure. For DNTT, a benzene ring structure with sulfur atoms conjugated with carbon atoms is verified by XPS analysis (Supporting Information, Figure S2).

Figure 1

Figure 1. (a) Schematic device structure of the ZnO–DNTT AAS device. (b) Photograph of the fabricated device. Scale bar = 200 μm. (c) Cross-sectional TEM image of the ZnO–DNTT heterojunction region. Scale bar = 20 nm. (d) ID–VG curves of p-type DNTT TFT and n-type ZnO TFT. The thicknesses of each channel are 50 and 29 nm at VD = ∓ 5 V, respectively. (e) ID–VG curves of ZnO–DNTT AAS devices at VD = 5 V. (f) Negative gm property of the AAS device at VD = 5 V. (g) ID–VG curves of ZnO–DNTT AAS devices with VD ranging from −5 and 5–30 V. Symbols indicate experimental data, and lines indicate device modeling fitting results.

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Figure 1(d) shows the ID–VG curves of thin-film transistors (TFTs) from individually fabricated DNTT and ZnO TFTs with typical electrical characteristics of depletion mode p-type and n-type semiconductor TFTs, respectively. The p-type DNTT TFT exhibited a subthreshold swing of 0.33 V/dec, a field-effect mobility of 2.3 cm2/V·s, and an on/off ratio of 106. For the ZnO n-type TFT, a subthreshold swing of 1.12 V/dec, a field-effect mobility of 48 cm2/V·s, and an on/off ratio of 107 were obtained. Swing values appear to be high in our devices because the gate dielectric thickness is 90 nm. The on/off ratio and field-effect mobility of our devices are comparable to or better than those of individual n-type ZnO TFT and p-type DNTT TFTs previously reported. (41−44) Furthermore, owing to the balance of these electrical characteristics between n- and p-type TFTs, the AAS devices fabricated with the combination of ZnO TFT and DNTT TFT showed symmetrical transfer properties.
The transfer characteristic of ZnO–DNTT AAS devices measured at VD = 5 V is shown in Figure 1(e). A PVR of ∼105 was obtained within a narrow turn-on region from −3 to 8 V. The AAS device showed a negative gm, which reached −20 nS at VDNTT = 5 V, as shown in Figure 1(f). Figure 1(g) shows the drain bias dependence of the AAS device. As VD increased, the peak voltage, peak current, and operation window of the AAS device increased, and a PVR of ∼106 was obtained at VD = 30 V. This is the highest PVR of an AAS device yet reported (102–105). (29−40,45,46) On the other hand, when VDNTT is negative (−5 V), the current does not flow because of the reverse bias barrier of the PN junction.
Figure 2 shows the operation mechanism of the AAS device. The electrical behavior of the AAS device can be easily understood if we interpret this device as three devices connected in series that are controlled by the same gate bias: n-type ZnO TFT–ZnO/DNTT PN junction–p-type DNTT TFT. When VG was lower than Vth of the ZnO TFT (Vth,n) (Figure 2(a)) or higher than Vth of the DNTT TFT (Vth,p) (Figure 2(c)), the final conductance of this series connected device was very low; that is, when one of two semiconductors is turned off, the carriers cannot flow across the depleted channel. Forward diode current can flow through the ZnO/DNTT heterojunction region only when the ZnO TFT and DNTT TFT regions are partially turned on. Thus, this device can only be turned on between Vth,n and Vth,p (ΔVON) (Figure 2(b)). As a result, the current flow increases rapidly at a certain bias and dissipates at the other bias, as shown in Figure 2(d). IPEAK position is defined as the highest current value at VPEAK, and the peak-to-valley ratio is defined as IPEAK over the lowest current outside of ΔVON.

Figure 2

Figure 2. Schematic diagram of the cross-sectional AAS device structures and band diagrams with carrier flows when (a) VG < Vth,n, (b) Vth,n < VG < Vth,p, and (c) Vth,p < VG. (d) Typical ID–VG curve of the AAS device.

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Physically, the drive current of this device is similar to the leakage current of an inverter consisting of a p-type DNTT TFT and an n-type ZnO TFT, but the current flux can be modulated by individually controlling the properties of an n-type TFT, a p-type TFT, and ZnO/DNTT heterojunctions. Figure 3(a) shows the outcome of device modulation with different ZnO channel thicknesses. As the ZnO channel thickness increases, the electron charge concentration tends to increase, so the Vth of ZnO TFTs decreases. (25,47) Accordingly, the turn-on range (ΔVON) of the AAS device can be modulated. By controlling the thickness of ZnO, IPEAK was modulated in proportion to ΔVON. In the DNTT channel, the hole charge concentration can also be varied by changing the thickness of the channels. (48)Figure 3(b) shows the ID–VG curves of AAS devices with different DNTT channel thicknesses. Because the Vth variability of individual ZnO TFTs was much larger than that of DNTT TFTs (Supporting Information, Figure S4(a–b)), the range of ΔVON modulation was higher for devices with different ZnO thicknesses than for those with different DNTT thicknesses. Meanwhile, even though there was a trade-off between IPEAK and ΔVON, very sharp and narrow regions of ΔVON could be achieved with extremely high PVRs above 103 in both cases.

Figure 3

Figure 3. ID–VG curves of the AAS device with different (a) thicknesses of ZnO (50 nm of DNTT), (b) thickness of DNTT (29 nm of ZnO), and (c) types of doping layer at VD = 5 V (29 and 50 nm of ZnO and DNTT, respectively).

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While the thickness change in the n-type or p-type region affected the Vth and current level, the peak current position was not changed significantly. In other words, shifting the range of the turn-on region of the device was limited. To find a way to shift the device turn-on region, an additional polymer-based doping layer was inserted between the ZnO and DNTT layers. Figure 3(c) shows the result of the doping layer insertion. We used polyethylenimine (PEI) (n-doping) and poly(acrylic acid) (PAA) (p-doping) as doping layers, which induced electrons and holes at both surfaces of ZnO and DNTT, respectively. With electron doping (PEI), the Vth of single-channel TFT devices shifts toward the negative bias side. Meanwhile, the Vth shifts toward the positive bias side with hole doping (PAA) (Supporting Information, Figure S4(c–d)). Figure 3(c) clearly shows that the range of the turn-on region of the device can be shifted by inserting the doping layer. In summary, we have identified various parameters that can be used to modulate the peak current level, peak position, and width of the turn-on region. With further optimization, we expect to realize a more sharply defined turn-on region at the specific design position.
The fabrication process appears to be relatively stable and shows promising scale-up feasibility. Figure 4(a) shows consistent ID–VG curves for 72 separate AAS devices in a single chip. To verify the stability and manufacturability of ZnO–DNTT AAS devices, the statistical data were extracted. Figure 4(b) shows the average PVR values measured over 180 days, having a consistent distribution within a 2 × 2 cm chip (inset of Figure 4(b) shows the optical photograph of this chip). Figure 4(c) shows the distributions of PVR values, VPEAK, and ΔVON. The coefficient of variation, CV = s/xm × 100%, where s is the standard deviation and xm is the average value, can be applied to quantify the distribution of data. (49) The CVs of the distributions for PVR, VPEAK, and ΔVON are 9.7%, 4.4%, and 3.4%, respectively. CVs of each distribution are within 10% for all devices measured from the same chip, which means the device distributions are reasonably tight even with the manufacturing process at university facilities (clean class 10000). Table 1 compares various AAS devices reported in the literature. Most of the devices fabricated with TMDCs used the exfoliation method, which is not suitable for practical large-area manufacturing processes. Some heterojunction devices were fabricated using organic semiconductors deposited using the evaporation method, but the operation voltages were very high. (45,46) Our ZnO–DNTT AAS device exhibited air-stable and uniform device properties with a reasonably tight distribution and can be fabricated with a low process temperature, which is very useful for monolithic or heterogeneous 3D integration.

Figure 4

Figure 4. (a) ID–VG curves for 72 separate AAS devices at VD = 30 V, in which thicknesses of ZnO and DNTT are 29 and 50 nm, respectively. (b) PVR of the AAS device over time (inset: 2 cm × 2 cm wafer with 72 AAS devices) and (c) the distributions of the PVR, VPEAK, and ΔVON from 72 AAS devices.

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Table 1. Comparison of AAS Devices
deviceJD [nA/μm]PVRfab. methodfab. T [°C]EOT [nm]|VD| [V]
ZnO–DNTT (this work)0.9–5.6105–106ALD and evaporation120905–30
Si (p+–i–n+) (29)0.004–22–10CMOS 250.05–0.7
Si (n+–p+–n+) (30)3.62CMOS 20.001
Si (p+–n+–p+) (31)20–1091–5.5CMOS80030.01–0.05
Si–Ge nanowire (32)0.22–27020–48CVD49520.2–0.8
GaSb–InAsSb nanowire (33)22001.6epitaxy500100.5
MoS2–WSe2 (36)30103exfoliation360>3001
SnSeS–BP (37)133102exfoliation 4.681
MoS2–BP (38)67103exfoliation2503001
ReS2–BP (39)4000105exfoliation2503.91
MoS2–pentacene (40)450103exfoliation10030010
PTCDI-C8-6T (45)0.25 × 104evaporation120>20060
PTCDI-C8–DNTT (46)0.05–0.6103–105evaporation175>35030–60
For more practical applications, circuit-level implementation strategies of ternary circuits are examined using the ZnO–DNTT AAS device model. The semiphysical analytical device model is developed using a series connection of n- and p-type TFT models and a PN junction model. The simulation result fits very well with the experimental data shown in Figure 1(g).
Conceptually, the ternary circuit using the AAS device can be simplified as shown in Figure 5(a). Three networks for pull-up (PU), pull-down (PD), and pull-middle (PM) are necessary to represent ternary states, and they are connected to VDD, VGND, and VDD/2 voltage sources, respectively. Compared with previous ternary circuit schemes (Supporting Information, Figure S5), an additional voltage source (VDD/2) and a PM network were added to provide an intermediate state. Recently, an inverter showing ternary characteristics using an organic-based AAS device has been reported. (46) In this scheme, the leakage current problem at the intermediate state still exists because both PU and PD are half turned on. In our scheme, devices in PU and PD networks turn off at the intermediate state, which is similar to that in a CMOS inverter circuit. Within the narrow operation window where both PU and PD networks are turned off, the AAS device is turned on to provide the intermediate state while avoiding the leakage current from VDD to VGND. In summary, three networks are used to represent three states in our scheme, and only one network is turned on for each state.

Figure 5

Figure 5. (a) Static gate design methodology for the proposed ternary circuit, (b) their truth table and switching table strategy, (c) device symbol and device structure of an AAS ternary unit cell, and (d) current transfer characteristics of an ideal AAS ternary unit cell model for EOT = 1 nm and W = L = 100 nm.

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The static ternary gate design methodology using this approach is shown schematically in Figure 5(b). The truth table is divided into three tables, which correspond to PU, PD, and PM networks. Note that the AAS device works only under a forward drain bias (VD = +5 V). When the drain bias is negative, there is no current flow, as shown in Figure 1(g). In this case, the transition between the PM and PU (or PD) network can be restricted if a reverse bias is applied to the AAS device during the transition. This problem can be overcome by adding an AAS device in the opposite direction as shown in Figure 5(c). Figure 5(d) shows the theoretically modeled I–V curves of an AAS unit cell, which shows bidirectional switching characteristics with VDD less than 2 V. For this modeling, the equivalent oxide thickness (EOT) of the gate dielectric is assumed to be 1 nm, and the channel length and width are assumed to be 100 nm to emulate the scaled device operation.
Using the AAS unit cell shown in Figure 5(c), an STI is designed to demonstrate the circuit level benefits of the ZnO–DNTT AAS device. Figure 6(a) shows the transition from a PU to PM network. With low VIN, the p-type device in the PU network is turned on and the AAS device in the PM network is turned off. As VIN increases, the p-type device is starting to turn off while the AAS device is starting to turn on. When the transition between the PU and PM network occurs, VOUT is changed from 2 V (VDD) to 1 V (VDD/2). The leakage current flows from the VDD node to the VDD/2 node during this state transition only, similar to that in a CMOS inverter. Likewise, Figure 6(b) shows the transition between the PM and PD network when VOUT is changed from 1 V (VDD/2) to 0 V (VGND). The voltage transfer characteristics (VTCs) and the leakage current are shown in Figure 6(c). In both cases, the leakage current flows only during the state transition, in which both networks (PU and PM or PM and PD) are turned on at the same time. As a result, the static power problem at the intermediate state of ternary logic can be minimized. In other STIs, leakage currents at the intermediate state are on the order of μA to nA, (19,25) but the leakage current of the STI with an AAS device is at the pA level. Overall, the static power of an STI with an AAS device can be reduced to a sub-nW level, which is ∼1/100 of the typical value for a CNTFET-based ternary STI (Supporting Information, Figure S6).

Figure 6

Figure 6. Proposed STI operation and its VTCs as VOUT changes from (a) 2 to 1 V and (b) 1 to 0 V and (c) whole VTC (symbol) with drive current (line).

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Using the above design strategy, various ternary module circuits such as STI, negative ternary inverter (NTI), positive ternary inverter (PTI) (Supporting Information, Figure S7), NMIN, NMAX (Supporting Information, Figure S8), SUM, CONS, and ANY (Supporting Information, Figure S9) were designed using the AAS devices. Integrating these module circuits, a ternary full adder was simulated. Figure 7(a) shows a ternary half adder designed by combining one SUM and one CONS gate. A ternary full adder is designed by combining two half adders and one ANY gate. (19,21) The truth tables of SUM, CONS, and ANY gates are shown in Figure 7(b). The transient responses of the ternary full adder obtained at 5 MHz frequency are shown in Figure 7(c). Because these devices are not fully optimized, some glitches remain; however, the overall logic functionality has been successfully confirmed, which indicates that ternary logic circuits of any size can be designed using our approach.

Figure 7

Figure 7. (a) Gate level of the ternary full adder, (b) truth tables of SUM, CONS, and ANY gates, and (c) transient responses of the proposed ternary full adder.

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The performance of our ternary full adder implemented with the ZnO–DNTT AAS device was evaluated and compared with other circuits having similar complexity using HSpice (Table 2). In all the circuits, four inverters were connected to the fan-out node, and all scaled physical dimensions were set to 100 nm (for binary CMOS, it was 90 nm). The CNTFET model of Stanford University (50) and the predictive technology model for a 90 nm CMOS (51) are used to evaluate other full adder circuits. For the binary ternary adder, 2-bit circuits are used for the comparison because the size of data of 1 trit is closest to that of 2 bits. (21,52)
Table 2. Comparison of Full Adder Circuits
logic architectureVDD [V]# Trpower [μW]delay [ps]PDP [aJ]
1-trit ternarythis work (L = W = 100 nm)2880.15799122
CNTFET (L = 100 nm)11101.07160172
2-bits binary90 nm CMOS2567.15120858
1560.09620019
Compared to the CNTFET-based 1-trit full adder, the proposed full adder has great advantages in terms of the number of transistors, power, and power–delay product, even at larger VDD. In particular, the power consumption is ∼7 times lower than that of the CNTFET-based full adder. Furthermore, the power consumption and PDP of the 1-trit full adder are superior to the 2-bit binary full adder; especially, the power consumption is ∼47 times lower than that of the binary full adder. The power consumption of the ternary circuit is even comparable to that of the optimal CMOS circuit at VDD = 1 V. Although the PDP of the ternary circuit is comparable to that of binary CMOS due to significant power saving, the delay needs to be improved further, by potentially optimizing parasitic components such as contact resistances or capacitances. Overall, we have confirmed that the proposed ternary circuits utilizing the AAS device can have technical advantages for extremely low power applications if the appropriate scaling of the AAS device can be achieved.

Conclusion

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A ZnO–DNTT AAS device and ternary unit cell design to overcome the well-known leakage current problem of ternary logic in the intermediate state has been successfully demonstrated with extremely low power operation capability. Using this device concept, the advantages of the ternary full adder over other ternary devices or even binary CMOS devices, especially in terms of power consumption, have been confirmed. Even though the operation voltage of the AAS device should be scaled down further for more scaled devices, this approach will expand the capabilities of ternary logic architecture, especially for low-power ternary logic systems monolithically integrated with binary logic systems.

Methods

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Fabrication Process and Electrical Characterization of ZnO–DNTT AAS Device

The 90 nm SiO2/p++ Si substrates (used as a back gate) were cleaned with acetone, isopropyl alcohol, and distilled water (DI) for 5 min in sequence by sonication. Then, ZnO layers were deposited using the atomic layer deposition (ALD) process at 120 °C using a diethyl zinc (DEZ) precursor and H2O oxidant. The thicknesses of ZnO varied from 19 to 50 nm by controlling the cycle of the ALD process. Then, the ZnO layers were patterned using photolithography and a wet etch process with 1% HCl solution diluted by DI. To perform chemical doping, the surface of active ZnO was submerged into a 0.2 wt % ethanol-diluted branched PEI (Sigma-Aldrich) or PAA (Sigma-Aldrich) solution for 3 h. Subsequently, the devices were cleaned with pure ethanol for a few seconds to prevent the excessive doping effect. For the p-type semiconductor, a DNTT (Sigma-Aldrich) layer was deposited to form a heterojunction structure using thermal evaporation at 25 °C. Patterning was performed using a shadow mask. The thicknesses of DNTT varied from 5 to 50 nm. Then, 70 nm thermally evaporated Au electrodes were deposited using the shadow mask process. While fabricating the heterojunction devices, ZnO and DNTT single-channel devices were also fabricated as references. Electrical characterization was performed using a semiconductor parameter analyzer (Keithley 4200) at 25 °C in ambient air.

Device and Logic Circuit Modeling

Device modeling and circuit synthesis were performed using HSpice (Synopsys). A semiphysical analytical TFT model was used to model the device characteristics of the ZnO–DNTT AAS device. (53) Transient response, power dissipation, and delay of ternary circuits were extracted using the developed ZnO–DNTT AAS device model and compared with the modeling results of the ternary circuits designed with the CNTFET model (50) and the predictive technology model for 90 nm CMOS. (51)

Supporting Information

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The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsnano.2c03523.

  • Fabrication process flow of the ZnO–DNTT AAS device, XPS analysis of ZnO and DNTT, transfer curves and transconductance of ZnO–DNTT AAS device dependence on voltage bias, transfer curves of ZnO and DNTT single TFT dependence on channel thickness and doping type, various STI schemes, comparison of STI operation, various ternary circuit designs and their operation (Figures S1–S9) and PM ternary device switching table (Table S1) (PDF)

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Author Information

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  • Corresponding Authors
    • Seokhyeong Kang - Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea;  Email: [email protected]
    • Byoung Hun Lee - Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea;  Orcidhttps://orcid.org/0000-0002-4540-7731;  Email: [email protected]
  • Authors
    • Yongsu Lee - Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
    • Sunmean Kim - Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
    • Ho-In Lee - Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
    • Seung-Mo Kim - Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
    • So-Young Kim - Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
    • Kiyung Kim - Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
    • Heejin Kwon - Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
    • Hae-Won Lee - Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
    • Hyeon Jun Hwang - Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of Korea
  • Notes
    The authors declare no competing financial interest.

Acknowledgments

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This work was partially supported by Creative Materials Discovery Program on Creative Multilevel Research Center (2017M3D1A1040834) and FEOL platform development program (2020M3F3A2A02082436) through the National Research Foundation of Korea (NRF), funded by the Ministry of Science and ICT, Korea.

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    Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technol. requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degrdn. due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000°C, 1.5 s, without adversely impacting the stack morphol. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielec. plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high m.p. which does not diffuse into dielecs. also minimizes the risk of contamination. To assess the device degrdn., simulations are carried out showing negligible stress transfer from BPR to the channel. This is exptl. validated when no systematic difference in the dc characteristics of CMOS without BPR vs. those in close proximity to floating W-BPR lines is obsd. Addnl., the resistance of the recessed W-BPR line is measured ~ 120 ω/μm for crit. dimension (CD) ~ 32 nm and height ~ 122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330°C, making Ru a candidate for via metalization to achieve low resistance contact strategy to BPR.
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  29. 29
    Kim, C.; Lee, Y.; Lee, S. Systematic Modulation of Negative-Differential Transconductance Effects for Gated P+-i-N+ Silicon Ultra-Thin Body Transistor. J. Appl. Phys. 2017, 121 (12), 124504,  DOI: 10.1063/1.4979213
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    29
    Systematic modulation of negative-differential transconductance effects for gated p+-i-n+ silicon ultra-thin body transistor
    Kim, Changmin; Lee, Youngmin; Lee, Sejoon
    Journal of Applied Physics (Melville, NY, United States) (2017), 121 (12), 124504/1-124504/4CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)
    The authors demonstrate the precise control of the neg.-differential transconductance (NDT) effects on a gated p+-i-n+ Si ultra-thin body transistor. The device clearly displays the N-shape transfer characteristic (i.e., NDT effect) at room temp., and the NDT behavior is fully based on the gate-modulation of the electrostatic junction characteristics. The position and the current level of the peak in the NDT region are systematically controllable when modulating the potential profile at the channel-source junction. Namely, the NDT effect can be systematically modulated through modifying the band-to-band tunneling condition by controlling both gate- and drain-bias voltages. In-depth analyses on the transport characteristics and transport mechanisms are discussed. (c) 2017 American Institute of Physics.
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  30. 30
    Naquin, C.; Lee, M.; Edwards, H.; Mathur, G.; Chatterjee, T.; Maggio, K. Gate Length and Temperature Dependence of Negative Differential Transconductance in Silicon Quantum Well Metal-Oxide-Semiconductor Field-Effect Transistors. J. Appl. Phys. 2015, 118 (12), 124505,  DOI: 10.1063/1.4931662
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    30
    Gate length and temperature dependence of negative differential transconductance in silicon quantum well metal-oxide-semiconductor field-effect transistors
    Naquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, Ken
    Journal of Applied Physics (Melville, NY, United States) (2015), 118 (12), 124505/1-124505/6CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)
    Introducing quantum transport into silicon transistors in a manner compatible with industrial fabrication has the potential to transform the performance horizons of large scale integrated silicon devices and circuits. Explicit quantum transport as evidenced by neg. differential transconductances (NDTCs) was obsd. in a set of quantum well (QW) transistors fabricated using industrial silicon complementary metal-oxide-semiconductor processing. Detailed gate length and temp. dependence characteristics of the NDTCs in these devices were measured. The QW potential was formed via lateral ion implantation doping on a com. 45 nm technol. node process line, and measurements of the transfer characteristics show NDTCs up to room temp. Gate length dependence of NDTCs shows a correlation of the interface channel length with the no. of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temp. dependence is consistent with partial freeze-out of carrier concn. against a degenerately doped background. (c) 2015 American Institute of Physics.
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  31. 31
    Kim, K. R.; Kim, H. H.; Song, K.-W.; Huh, J. I.; Lee, J. D.; Park, B.-G. Field-Induced Interband Tunneling Effect Transistor (FITET) with Negative-Differential Transconductance and Negative-Differential Conductance. IEEE Transactions on Nanotechnology 2005, 4 (3), 317– 321,  DOI: 10.1109/TNANO.2005.847008
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    Zhang, P.; Le, S. T.; Hou, X.; Zaslavsky, A.; Perea, D. E.; Dayeh, S. A.; Picraux, S. T. Strong Room-Temperature Negative Transconductance in an Axial Si/Ge Hetero-Nanowire Tunneling Field-Effect Transistor. Appl. Phys. Lett. 2014, 105 (6), 062106,  DOI: 10.1063/1.4892950
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    32
    Strong room-temperature negative transconductance in an axial Si/Ge hetero-nanowire tunneling field-effect transistor
    Zhang, Peng; Le, Son T.; Hou, Xiaoxiao; Zaslavsky, A.; Perea, Daniel E.; Dayeh, Shadi A.; Picraux, S. T.
    Applied Physics Letters (2014), 105 (6), 062106/1-062106/4CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
    The authors report on room-temp. neg. transconductance (NTC) in axial Si/Ge hetero-nanowire tunneling field-effect transistors. The NTC produces a current peak-to-valley ratio >45, a high value for a Si-based device. The authors characterize the NTC over a range of gate VG and drain VD voltages, finding that NTC persists down to VD = -50 mV. The phys. mechanism responsible for the NTC is the VG-induced depletion in the p-Ge section that eventually reduces the max. elec. field that triggers the tunneling ID, as confirmed via three-dimensional (3D) technol. computer-aided design simulations. (c) 2014 American Institute of Physics.
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  33. 33
    Dey, A. W.; Svensson, J.; Ek, M.; Lind, E.; Thelander, C.; Wernersson, L.-E. Combining Axial and Radial Nanowire Heterostructures: Radial Esaki Diodes and Tunnel Field-Effect Transistors. Nano Lett. 2013, 13 (12), 5919– 5924,  DOI: 10.1021/nl4029494
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    33
    Combining Axial and Radial Nanowire Heterostructures: Radial Esaki Diodes and Tunnel Field-Effect Transistors
    Dey, Anil W.; Svensson, Johannes; Ek, Martin; Lind, Erik; Thelander, Claes; Wernersson, Lars-Erik
    Nano Letters (2013), 13 (12), 5919-5924CODEN: NALEFD; ISSN:1530-6984. (American Chemical Society)
    The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit. The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Also, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties. In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a const. drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects; however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require addnl. chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addn. to design advantages of a radial transistor architecture, the authors in this work illustrate the benefit in terms of drive current per unit chip area and compare the exptl. data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the elec. data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. The data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm2, than the max. peak current of axial GaSb/InAs-(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm2, while their axial counterparts at most carry Jpeak = 77 kA/cm2, normalized to the largest cross-sectional area of the nanowire.
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  34. 34
    Ganjipour, B.; Dey, A. W.; Borg, B. M.; Ek, M.; Pistol, M.-E.; Dick, K. A.; Wernersson, L.-E.; Thelander, C. High Current Density Esaki Tunnel Diodes Based on GaSb-InAsSb Heterostructure Nanowires. Nano Lett. 2011, 11 (10), 4222– 4226,  DOI: 10.1021/nl202180b
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    34
    High Current Density Esaki Tunnel Diodes Based on GaSb-InAsSb Heterostructure Nanowires
    Ganjipour, Bahram; Dey, Anil W.; Borg, B. Mattias; Ek, Martin; Pistol, Mats-Erik; Dick, Kimberly A.; Wernersson, Lars-Erik; Thelander, Claes
    Nano Letters (2011), 11 (10), 4222-4226CODEN: NALEFD; ISSN:1530-6984. (American Chemical Society)
    The authors present elec. characterization of broken gap GaSb-InAsSb nanowire heterojunctions. Esaki diode characteristics with max. reverse current of 1750 kA/cm2 at 0.50 V, max. peak current of 67 kA/cm2 at 0.11 V, and peak-to-valley ratio (PVR) of 2.1 were obtained at room temp. The reverse c.d. is comparable to that of state-of-the-art tunnel diodes based on heavily doped p-n junctions. However, the GaSb-InAsSb diodes studied in this work do not rely on heavy doping, which permits studies of transport mechanisms in simple transistor structures processed with high-κ gate dielecs. and top-gates. Such processing results in devices with improved PVR (3.5) and stability of the elec. properties.
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  35. 35
    Carnevale, S. D.; Marginean, C.; Phillips, P. J.; Kent, T. F.; Sarwar, A. T. M. G.; Mills, M. J.; Myers, R. C. Coaxial Nanowire Resonant Tunneling Diodes from Non-Polar AlN/GaN on Silicon. Appl. Phys. Lett. 2012, 100 (14), 142115,  DOI: 10.1063/1.3701586
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    35
    Coaxial nanowire resonant tunneling diodes from non-polar AlN/GaN on silicon
    Carnevale, S. D.; Marginean, C.; Phillips, P. J.; Kent, T. F.; Sarwar, A. T. M. G.; Mills, M. J.; Myers, R. C.
    Applied Physics Letters (2012), 100 (14), 142115/1-142115/4CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
    Resonant tunneling diodes are formed using AlN/GaN core-shell nanowire heterostructures grown by plasma assisted MBE on n-Si(111) substrates. By a coaxial geometry, these devices take advantage of non-polar (m-plane) nanowire sidewalls. Device modeling predicts non-polar orientation should enhance resonant tunneling compared to a polar structure, and that AlN double barriers will lead to higher peak-to-valley current ratios compared to AlGaN barriers. Elec. measurements of ensembles of nanowires show neg. differential resistance appearing only at cryogenic temp. Individual nanowire measurements show neg. differential resistance at room temp. with peak c.d. of 5 × 105 A/cm2. (c) 2012 American Institute of Physics.
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  36. 36
    Nourbakhsh, A.; Zubair, A.; Dresselhaus, M. S.; Palacios, T. Transport Properties of a MoS2/WSe2 Heterojunction Transistor and Its Potential for Application. Nano Lett. 2016, 16 (2), 1359– 1366,  DOI: 10.1021/acs.nanolett.5b04791
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    36
    Transport Properties of a MoS2/WSe2 Heterojunction Transistor and Its Potential for Application
    Nourbakhsh, Amirhasan; Zubair, Ahmad; Dresselhaus, Mildred S.; Palacios, Tomas
    Nano Letters (2016), 16 (2), 1359-1366CODEN: NALEFD; ISSN:1530-6984. (American Chemical Society)
    This paper studies band-to-band tunneling in the transverse and lateral directions of van der Waals MoS2/WSe2 heterojunctions. We observe room-temp. neg. differential resistance (NDR) in a heterojunction diode comprised of few-layer WSe2 stacked on multilayer MoS2. The presence of NDR is attributed to the lateral band-to-band tunneling at the edge of the MoS2/WSe2 heterojunction. The backward tunneling diode shows an av. conductance slope of 75 mV/dec with a high curvature coeff. of 62 V-1. Assocd. with the tunnel-diode characteristics, a pos.-to-neg. transconductance in the MoS2/WSe2 heterojunction transistors is obsd. The transition is induced by strong interlayer coupling between the films, which results in charge d. and energy-band modulation. The sign change in transconductance is particularly useful for multivalued logic (MVL) circuits, and we therefore propose and demonstrate for the first time an MVL-inverter that shows three levels of logic using one pair of p-type transistors.
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    Huang, M.; Li, S.; Zhang, Z.; Xiong, X.; Li, X.; Wu, Y. Multifunctional High-Performance van Der Waals Heterostructures. Nat. Nanotechnol. 2017, 12 (12), 1148– 1154,  DOI: 10.1038/nnano.2017.208
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    Multifunctional high-performance van der Waals heterostructures
    Huang, Mingqiang; Li, Shengman; Zhang, Zhenfeng; Xiong, Xiong; Li, Xuefei; Wu, Yanqing
    Nature Nanotechnology (2017), 12 (12), 1148-1154CODEN: NNAABX; ISSN:1748-3387. (Nature Research)
    A range of novel two-dimensional materials have been actively explored for More Moore and More-than-Moore device applications because of their ability to form van der Waals heterostructures with unique electronic properties. However, most of the reported electronic devices exhibit insufficient control of multifunctional operations. Here, we leverage the band-structure alignment properties of narrow-bandgap black phosphorus and large-bandgap molybdenum disulfide to realize vertical heterostructures with an ultrahigh rectifying ratio approaching 106 and on-off ratio up to 107. Furthermore, we design and fabricate tunable multivalue inverters, in which the output logic state and window of the mid-logic can be controlled by specific pairs of channel length and, most importantly, by the elec. field, which shifts the band-structure alignment across the heterojunction. Finally, high gains over 150 are achieved in the inverters with optimized device geometries, showing great potential for future logic applications.
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    Lv, W.; Fu, X.; Luo, X.; Lv, W.; Cai, J.; Zhang, B.; Wei, Z.; Liu, Z.; Zeng, Z. Multistate Logic Inverter Based on Black Phosphorus/SnSeS Heterostructure. Adv. Electron. Mater. 2019, 5 (1), 1800416,  DOI: 10.1002/aelm.201800416
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    Xiong, X.; Kang, J.; Hu, Q.; Gu, C.; Gao, T.; Li, X.; Wu, Y. Reconfigurable Logic-in-Memory and Multilingual Artificial Synapses Based on 2D Heterostructures. Adv. Funct. Mater. 2020, 30 (11), 1909645,  DOI: 10.1002/adfm.201909645
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    Reconfigurable logic-in-memory and multilingual artificial synapses based on 2D heterostructures
    Xiong, Xiong; Kang, Jiyang; Hu, Qianlan; Gu, Chengru; Gao, Tingting; Li, Xuefei; Wu, Yanqing
    Advanced Functional Materials (2020), 30 (11), 1909645CODEN: AFMDC6; ISSN:1616-301X. (Wiley-VCH Verlag GmbH & Co. KGaA)
    Nonvolatile logic devices have attracted intensive research attentions recently for energy efficiency computing, where data computing and storage can be realized in the same device structure. Various approaches have been adopted to build such devices; however, the functionality and versatility are still very limited. Here, 2-dimensional van der Waals heterostructures based on direct band gap materials black phosphorus and rhenium disulfide for the nonvolatile ternary logic operations is demonstrated for the first time with the ultrathin oxide layer from the black phosphorus serving as the charge trapping as well as band-to-band tunneling layer. Furthermore, an artificial electronic synapse based on this heterostructure is demonstrated to mimic trilingual synaptic response by changing the input base voltage. Besides, artificial neural network simulation based on the electronic synaptic arrays using the handwritten digits data sets demonstrates a high recognition accuracy of 91.3%. This work provides a path toward realizing multifunctional nonvolatile logic-in-memory applications based on novel 2D heterostructures.
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  40. 40
    Dong, J.; Liu, F.; Wang, F.; Wang, J.; Li, M.; Wen, Y.; Wang, L.; Wang, G.; He, J.; Jiang, C. Configuration-Dependent Anti-Ambipolar van Der Waals p–n Heterostructures Based on Pentacene Single Crystal and MoS2. Nanoscale 2017, 9 (22), 7519– 7525,  DOI: 10.1039/C7NR01822C
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    40
    Configuration-dependent anti-ambipolar van der Waals p-n heterostructures based on pentacene single crystal and MoS2
    Dong, Ji; Liu, Fengjing; Wang, Feng; Wang, Jiawei; Li, Molin; Wen, Yao; Wang, Liang; Wang, Gongtang; He, Jun; Jiang, Chao
    Nanoscale (2017), 9 (22), 7519-7525CODEN: NANOHL; ISSN:2040-3372. (Royal Society of Chemistry)
    Recently, van der Waals heterostructures (vdWHs) have trigged intensive interest due to their novel electronic and optoelectronic properties. The vdWHs could be achieved by stacking two dimensional layered materials (2DLMs) on top of another and vertically kept by van der Waals forces. Furthermore, org. semiconductors are also known to interact via van der Waals forces, which offer an alternative for the fabrication of org.-inorg. p-n vdWHs. However, the performances of org.-inorg. p-n vdWHs produced so far are rather poor, owing to the unmatched elec. property between the 2DLMs and org. polycryst. films. To make improvements in such novel heterostructure architectures, here we adopt high quality org. single crystals instead of polycryst. films to construct a pentacene/MoS2 p-n vdWH. The vdWHs show a much higher c.d. and better anti-ambipolar characteristics with a highest transconductance of 211 nS. Moreover, device configuration-dependent transfer characteristics are demonstrated and a mechanism of a gate bias modulated vertical space charge zone existing at the vertical p-n vdWHs interface is proposed. These findings provide a new route to optimize the org.-inorg. p-n vdWHs and a guideline for studying the intrinsic properties of vdWHs.
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    Li, S.; Chen, X.; Liu, L.; Zeng, Z.; Chang, S.; Wang, H.; Wu, H.; Long, S.; Liu, C. Micron Channel Length ZnO Thin Film Transistors Using Bilayer Electrodes. J. Colloid Interface Sci. 2022, 622, 769– 779,  DOI: 10.1016/j.jcis.2022.04.016
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    Micron channel length ZnO thin film transistors using bilayer electrodes
    Li, Sizhe; Chen, Xue; Liu, Li; Zeng, Zhiyu; Chang, Sheng; Wang, Hao; Wu, Hao; Long, Shibing; Liu, Chang
    Journal of Colloid and Interface Science (2022), 622 (), 769-779CODEN: JCISA5; ISSN:0021-9797. (Elsevier B.V.)
    Micro light-emitting diodes (Micro-LEDs) are currently attracting more and more attention. Thin film transistors (TFTs) with micron channel lengths can be used to drive Micro-LEDs. The key parameters of TFTs, such as mobility, ION/IOFF and threshold voltage, still need to be improved. In this study, we propose and exptl. demonstrate ZnO TFTs using bilayer electrodes to overcome the short channel effects when the channel length is scaled down to 3μm. Ti, Mo and Sn interlayers not only serve as diffusion barriers to prohibit migration of Cu atoms from the top electrodes, but also enhance adhesive energy of the metal electrodes on ZnO channel layers. ZnO TFTs using Cu/Ti bilayer electrodes exhibit the best performance, e.g., a high mobility of 45.3 cm2V-1s-1, a high ION/IOFF ratio of 4.28 x 109, a low subthreshold of 0.24 V/dec and a proper threshold voltage of 1.13 V. The high mobility can be attributed to a significant decrease of the barrier height and a slight narrowing of the space charge layer, and the high ratio of ION/IOFF is concerned with the high electron concn. under an ON-state condition. Thus, ZnO TFTs using Cu/Ti bilayer electrodes can be used in next-generation displays.
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    Li, H.; Han, D.; Dong, J.; Yi, Z.; Zhou, X.; Zhang, S.; Zhang, X.; Wang, Y. Enhanced Performance of Atomic Layer Deposited Thin-Film Transistors With High-Quality ZnO/Al2O3 Interface. IEEE Trans. Electron Devices 2020, 67 (2), 518– 523,  DOI: 10.1109/TED.2019.2957048
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    Enhanced performance of atomic layer deposited thin-film transistors with high-quality ZnO/Al2O3 interface
    Li, Huijin; Han, Dedong; Dong, Junchen; Yi, Zhuang; Zhou, Xiaobin; Zhang, Shengdong; Zhang, Xing; Wang, Yi
    IEEE Transactions on Electron Devices (2020), 67 (2), 518-523CODEN: IETDAI; ISSN:1557-9646. (Institute of Electrical and Electronics Engineers)
    We fabricated ZnO channel/Al2O3 gate dielec. thin-film transistors (TFTs) by at. layer deposition (ALD) continuous growth process. The effects of the channel and the dielec. continuous growth on the performance of TFTs were investigated. Compared with noncontinuous growth ZnO/Al2O3 films, continuous growth ZnO/Al2O3 films with no obvious buffer layer and less residual O-H bonds possess superior ZnO/Al2O3 interface quality. The continuous growth TFTs exhibit a field-effect mobility of 19.6 cm2 V-1s-1, a subthreshold swing of 0.13 V dec-1, a high ION/IOFF of 4.1 x 109, a hysteresis window of 0.09 V, and an excellent uniformity of elec. characteristics. Continuous growth TFTs also demonstrate better stability with minor shifts of Vth 0.6 V [pos. bias stress (PBS)] and Vth - 0.3 V [neg. bias stress (NBS)]. The faster falling rates of activation energy for continuous growth TFTs indicate that the total trap d. is reduced through the continuous growth of active layer and dielec. layer. Our results suggest that the ALD-based continuous growth process could enhance the performance of TFTs.
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  43. 43
    Acharya, R.; Günder, D.; Breuer, T.; Schmitz, G.; Klauk, H.; Witte, G. Stability of Organic Thin-Film Transistors Based on Ultrathin Films of Dinaphtho[2,3-b:2′,3′-f]Thieno[3,2- b]Thiophene (DNTT). Journal of Materials Chemistry C 2021, 9 (1), 270– 280,  DOI: 10.1039/D0TC04554C
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    Stability of organic thin-film transistors based on ultrathin films of dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT)
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    Journal of Materials Chemistry C: Materials for Optical and Electronic Devices (2021), 9 (1), 270-280CODEN: JMCCCX; ISSN:2050-7534. (Royal Society of Chemistry)
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  • Abstract

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    Figure 1

    Figure 1. (a) Schematic device structure of the ZnO–DNTT AAS device. (b) Photograph of the fabricated device. Scale bar = 200 μm. (c) Cross-sectional TEM image of the ZnO–DNTT heterojunction region. Scale bar = 20 nm. (d) ID–VG curves of p-type DNTT TFT and n-type ZnO TFT. The thicknesses of each channel are 50 and 29 nm at VD = ∓ 5 V, respectively. (e) ID–VG curves of ZnO–DNTT AAS devices at VD = 5 V. (f) Negative gm property of the AAS device at VD = 5 V. (g) ID–VG curves of ZnO–DNTT AAS devices with VD ranging from −5 and 5–30 V. Symbols indicate experimental data, and lines indicate device modeling fitting results.

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    Figure 2

    Figure 2. Schematic diagram of the cross-sectional AAS device structures and band diagrams with carrier flows when (a) VG < Vth,n, (b) Vth,n < VG < Vth,p, and (c) Vth,p < VG. (d) Typical ID–VG curve of the AAS device.

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    Figure 3

    Figure 3. ID–VG curves of the AAS device with different (a) thicknesses of ZnO (50 nm of DNTT), (b) thickness of DNTT (29 nm of ZnO), and (c) types of doping layer at VD = 5 V (29 and 50 nm of ZnO and DNTT, respectively).

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    Figure 4

    Figure 4. (a) ID–VG curves for 72 separate AAS devices at VD = 30 V, in which thicknesses of ZnO and DNTT are 29 and 50 nm, respectively. (b) PVR of the AAS device over time (inset: 2 cm × 2 cm wafer with 72 AAS devices) and (c) the distributions of the PVR, VPEAK, and ΔVON from 72 AAS devices.

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    Figure 5

    Figure 5. (a) Static gate design methodology for the proposed ternary circuit, (b) their truth table and switching table strategy, (c) device symbol and device structure of an AAS ternary unit cell, and (d) current transfer characteristics of an ideal AAS ternary unit cell model for EOT = 1 nm and W = L = 100 nm.

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    Figure 6

    Figure 6. Proposed STI operation and its VTCs as VOUT changes from (a) 2 to 1 V and (b) 1 to 0 V and (c) whole VTC (symbol) with drive current (line).

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    Figure 7

    Figure 7. (a) Gate level of the ternary full adder, (b) truth tables of SUM, CONS, and ANY gates, and (c) transient responses of the proposed ternary full adder.

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      There is no corresponding record for this reference.
    21. 21
      Heo, S.; Kim, S.; Kim, K.; Lee, H.; Kim, S.-Y.; Kim, Y. J.; Kim, S. M.; Lee, H.-I.; Lee, S.; Kim, K. R.; Kang, S.; Lee, B. H. Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors. IEEE Electron Device Lett. 2018, 39 (12), 1948– 1951,  DOI: 10.1109/LED.2018.2874055
      21
      Ternary full adder using multi-threshold voltage graphene barristors
      Heo, Sunwoo; Kim, Sunmean; Kim, Kiyung; Lee, Hyeji; Kim, So-Young; Kim, Yun Ji; Kim, Seung Mo; Lee, Ho-In; Lee, Segi; Kim, Kyung Rok; Kang, Seokhyeong; Lee, Byoung Hun
      IEEE Electron Device Letters (2018), 39 (12), 1948-1951CODEN: EDLEDZ; ISSN:1558-0563. (Institute of Electrical and Electronics Engineers)
      Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ∼10-16 J, which is comparable to the binary equiv. circuit. The ternary full adder was modeled using device parameters extd. from the exptl. demonstrated multi-Vth ternary graphene barristors.
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    22. 22
      Kim, S.-Y.; Heo, S.; Kim, K.; Son, M.; Kim, S.-M.; Lee, H.-I.; Lee, Y.; Hwang, H. J.; Ham, M.-H.; Lee, B. H. Demonstration of Ternary Devices and Circuits Using Dual Channel Graphene Barristors. In 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL); IEEE: Fredericton, NB, Canada, 2019; pp 25– 30, DOI: 10.1109/ISMVL.2019.00013 .
      There is no corresponding record for this reference.
    23. 23
      Lee, Y.; Kim, S.-M.; KIM, K.; Kim, S.-Y.; Lee, H.-I.; Kwon, H.; Lee, H.-W.; Kim, C.; Some, S.; Hwang, H. J.; Lee, B. H. Dual-Channel P-Type Ternary DNTT–Graphene Barristor. Submitted to Sci. Rep. 2022.
      There is no corresponding record for this reference.
    24. 24
      Lee, L.; Hwang, J.; Jung, J. W.; Kim, J.; Lee, H.-I.; Heo, S.; Yoon, M.; Choi, S.; Van Long, N.; Park, J.; Jeong, J. W.; Kim, J.; Kim, K. R.; Kim, D. H.; Im, S.; Lee, B. H.; Cho, K.; Sung, M. M. ZnO Composite Nanolayer with Mobility Edge Quantization for Multi-Value Logic Transistors. Nat. Commun. 2019, 10 (1), 1998,  DOI: 10.1038/s41467-019-09998-x
      24
      ZnO composite nanolayer with mobility edge quantization for multi-value logic transistors
      Lee Lynn; Jung Jin Won; Kim Jongchan; Van Long Nguyen; Park Jinseon; Sung Myung Mo; Hwang Jeongwoon; Kim Jiyoung; Cho Kyeongjae; Hwang Jeongwoon; Lee Ho-In; Heo Sunwoo; Lee Byoung Hun; Yoon Minho; Im Seongil; Choi Sungju; Kim Dae Hwan; Jeong Jae Won; Kim Kyung Rok
      Nature communications (2019), 10 (1), 1998 ISSN:.
      A quantum confined transport based on a zinc oxide composite nanolayer that has conducting states with mobility edge quantization is proposed and was applied to develop multi-value logic transistors with stable intermediate states. A composite nanolayer with zinc oxide quantum dots embedded in amorphous zinc oxide domains generated quantized conducting states at the mobility edge, which we refer to as "mobility edge quantization". The unique quantized conducting state effectively restricted the occupied number of carriers due to its low density of states, which enable current saturation. Multi-value logic transistors were realized by applying a hybrid superlattice consisting of zinc oxide composite nanolayers and organic barriers as channels in the transistor. The superlattice channels produced multiple states due to current saturation of the quantized conducting state in the composite nanolayers. Our multi-value transistors exhibited excellent performance characteristics, stable and reliable operation with no current fluctuation, and adjustable multi-level states.
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    25. 25
      Kim, S.; Kim, K.; Kim, A. R.; Lee, H.; Lee, Y.; Kim, S.; Yu, S. H.; Lee, H.; Hwang, H. J.; Sung, M. M.; Lee, B. H. Operation Principles of ZnO/Al2O3-AlDMP/ZnO Stacked-Channel Ternary Thin-Film Transistor. Adv. Electron. Mater. 2021, 7 (6), 2100247,  DOI: 10.1002/aelm.202100247
      25
      Operation Principles of ZnO/Al2O3-AlDMP/ZnO Stacked-Channel Ternary Thin-Film Transistor
      Kim, So-Young; Kim, Kiyung; Kim, A. Reum; Lee, Ho-In; Lee, Yongsu; Kim, Seung-Mo; Yu, Sung Ho; Lee, Hae-Won; Hwang, Hyeon Jun; Sung, Myung Mo; Lee, Byoung Hun
      Advanced Electronic Materials (2021), 7 (6), 2100247CODEN: AEMDBW; ISSN:2199-160X. (Wiley-VCH Verlag GmbH & Co. KGaA)
      For many decades, novel devices demonstrating step-wise current-voltage characteristic at room temp. have been pursued to realize multi-valued logic computing that has significant advantages such as extremely low power consumption and high-d. information-processing capability. Recently, a novel ternary logic transistor has been constructed using an ultrathin ZnO/Al2O3-AlDMP/ZnO channel exhibiting a mobility edge-quantized conduction for the intermediate current level. This study investigates the operation principle of the ternary device using ZnO/Al2O3-AlDMP/ZnO stack and concludes that the first ZnO layer controls the level of the intermediate current, while the second ZnO layer controls the threshold voltage of the ternary device. These controllable elec. properties of the intermediate state of the ternary device have been applied to an n-type resistive-load std. ternary inverter, demonstrating the feasibility to achieve a ternary logic circuit consuming extremely low power with an optimal noise margin.
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    26. 26
      Shim, C.-H.; Heo, S.; Noh, J.; Kim, Y. J.; Kim, S.-Y.; Khan, A. K.; Lee, B. H. Design of Ratioless Ternary Inverter Using Graphene Barristor. In 2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) ; 2016; pp 23– 30, DOI: 10.1109/ISMVL.2016.51 .
      There is no corresponding record for this reference.
    27. 27
      Gupta, A.; Kundu, S.; Teugels, L.; Bommels, J.; Adelmann, C.; Heylen, N.; Jamieson, G.; Pedreira, O. V.; Ciofi, I.; Chava, B.; Wilson, C. J.; Tokei, Z. High-Aspect-Ratio Ruthenium Lines for Buried Power Rail. In 2018 IEEE International Interconnect Technology Conference (IITC) ; 2018; pp 4– 6, DOI: 10.1109/IITC.2018.8430415 .
      There is no corresponding record for this reference.
    28. 28
      Gupta, A.; Pedreira, O. V.; Arutchelvan, G.; Zahedmanesh, H.; Devriendt, K.; Mertens, H.; Tao, Z.; Ritzenthaler, R.; Wang, S.; Radisic, D.; Kenis, K.; Teugels, L.; Sebai, F.; Lorant, C.; Jourdan, N.; Chan, B. T.; Subramanian, S.; Schleicher, F.; Hopf, T.; Peter, A. P. Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling. IEEE Trans. Electron Devices 2020, 67 (12), 5349– 5354,  DOI: 10.1109/TED.2020.3033510
      28
      Buried power rail integration with FinFETs for ultimate CMOS scaling
      Gupta, Anshul; Pedreira, Olalla Varela; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, Katia; Mertens, Hans; Tao, Zheng; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, Boon Teik; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony Premkumar; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Xiuju; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Litta, Eugenio Dentoni; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, Noemie; Sepulveda, A.; Mertens, Sofie; Kim, Min-Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Christel; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano, Efrain; Mitard, Jerome; Wilson, Christopher J.; Holsteyns, Frank; Boemmels, Juergen; Demuynck, Steven; Tokei, Zsolt; Horiguchi, Naoto
      IEEE Transactions on Electron Devices (2020), 67 (12), 5349-5354CODEN: IETDAI; ISSN:1557-9646. (Institute of Electrical and Electronics Engineers)
      Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technol. requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degrdn. due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000°C, 1.5 s, without adversely impacting the stack morphol. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielec. plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high m.p. which does not diffuse into dielecs. also minimizes the risk of contamination. To assess the device degrdn., simulations are carried out showing negligible stress transfer from BPR to the channel. This is exptl. validated when no systematic difference in the dc characteristics of CMOS without BPR vs. those in close proximity to floating W-BPR lines is obsd. Addnl., the resistance of the recessed W-BPR line is measured ~ 120 ω/μm for crit. dimension (CD) ~ 32 nm and height ~ 122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330°C, making Ru a candidate for via metalization to achieve low resistance contact strategy to BPR.
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    29. 29
      Kim, C.; Lee, Y.; Lee, S. Systematic Modulation of Negative-Differential Transconductance Effects for Gated P+-i-N+ Silicon Ultra-Thin Body Transistor. J. Appl. Phys. 2017, 121 (12), 124504,  DOI: 10.1063/1.4979213
      29
      Systematic modulation of negative-differential transconductance effects for gated p+-i-n+ silicon ultra-thin body transistor
      Kim, Changmin; Lee, Youngmin; Lee, Sejoon
      Journal of Applied Physics (Melville, NY, United States) (2017), 121 (12), 124504/1-124504/4CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)
      The authors demonstrate the precise control of the neg.-differential transconductance (NDT) effects on a gated p+-i-n+ Si ultra-thin body transistor. The device clearly displays the N-shape transfer characteristic (i.e., NDT effect) at room temp., and the NDT behavior is fully based on the gate-modulation of the electrostatic junction characteristics. The position and the current level of the peak in the NDT region are systematically controllable when modulating the potential profile at the channel-source junction. Namely, the NDT effect can be systematically modulated through modifying the band-to-band tunneling condition by controlling both gate- and drain-bias voltages. In-depth analyses on the transport characteristics and transport mechanisms are discussed. (c) 2017 American Institute of Physics.
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    30. 30
      Naquin, C.; Lee, M.; Edwards, H.; Mathur, G.; Chatterjee, T.; Maggio, K. Gate Length and Temperature Dependence of Negative Differential Transconductance in Silicon Quantum Well Metal-Oxide-Semiconductor Field-Effect Transistors. J. Appl. Phys. 2015, 118 (12), 124505,  DOI: 10.1063/1.4931662
      30
      Gate length and temperature dependence of negative differential transconductance in silicon quantum well metal-oxide-semiconductor field-effect transistors
      Naquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, Ken
      Journal of Applied Physics (Melville, NY, United States) (2015), 118 (12), 124505/1-124505/6CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)
      Introducing quantum transport into silicon transistors in a manner compatible with industrial fabrication has the potential to transform the performance horizons of large scale integrated silicon devices and circuits. Explicit quantum transport as evidenced by neg. differential transconductances (NDTCs) was obsd. in a set of quantum well (QW) transistors fabricated using industrial silicon complementary metal-oxide-semiconductor processing. Detailed gate length and temp. dependence characteristics of the NDTCs in these devices were measured. The QW potential was formed via lateral ion implantation doping on a com. 45 nm technol. node process line, and measurements of the transfer characteristics show NDTCs up to room temp. Gate length dependence of NDTCs shows a correlation of the interface channel length with the no. of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temp. dependence is consistent with partial freeze-out of carrier concn. against a degenerately doped background. (c) 2015 American Institute of Physics.
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    31. 31
      Kim, K. R.; Kim, H. H.; Song, K.-W.; Huh, J. I.; Lee, J. D.; Park, B.-G. Field-Induced Interband Tunneling Effect Transistor (FITET) with Negative-Differential Transconductance and Negative-Differential Conductance. IEEE Transactions on Nanotechnology 2005, 4 (3), 317– 321,  DOI: 10.1109/TNANO.2005.847008
      There is no corresponding record for this reference.
    32. 32
      Zhang, P.; Le, S. T.; Hou, X.; Zaslavsky, A.; Perea, D. E.; Dayeh, S. A.; Picraux, S. T. Strong Room-Temperature Negative Transconductance in an Axial Si/Ge Hetero-Nanowire Tunneling Field-Effect Transistor. Appl. Phys. Lett. 2014, 105 (6), 062106,  DOI: 10.1063/1.4892950
      32
      Strong room-temperature negative transconductance in an axial Si/Ge hetero-nanowire tunneling field-effect transistor
      Zhang, Peng; Le, Son T.; Hou, Xiaoxiao; Zaslavsky, A.; Perea, Daniel E.; Dayeh, Shadi A.; Picraux, S. T.
      Applied Physics Letters (2014), 105 (6), 062106/1-062106/4CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
      The authors report on room-temp. neg. transconductance (NTC) in axial Si/Ge hetero-nanowire tunneling field-effect transistors. The NTC produces a current peak-to-valley ratio >45, a high value for a Si-based device. The authors characterize the NTC over a range of gate VG and drain VD voltages, finding that NTC persists down to VD = -50 mV. The phys. mechanism responsible for the NTC is the VG-induced depletion in the p-Ge section that eventually reduces the max. elec. field that triggers the tunneling ID, as confirmed via three-dimensional (3D) technol. computer-aided design simulations. (c) 2014 American Institute of Physics.
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    33. 33
      Dey, A. W.; Svensson, J.; Ek, M.; Lind, E.; Thelander, C.; Wernersson, L.-E. Combining Axial and Radial Nanowire Heterostructures: Radial Esaki Diodes and Tunnel Field-Effect Transistors. Nano Lett. 2013, 13 (12), 5919– 5924,  DOI: 10.1021/nl4029494
      33
      Combining Axial and Radial Nanowire Heterostructures: Radial Esaki Diodes and Tunnel Field-Effect Transistors
      Dey, Anil W.; Svensson, Johannes; Ek, Martin; Lind, Erik; Thelander, Claes; Wernersson, Lars-Erik
      Nano Letters (2013), 13 (12), 5919-5924CODEN: NALEFD; ISSN:1530-6984. (American Chemical Society)
      The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit. The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Also, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties. In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a const. drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects; however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require addnl. chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addn. to design advantages of a radial transistor architecture, the authors in this work illustrate the benefit in terms of drive current per unit chip area and compare the exptl. data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the elec. data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. The data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm2, than the max. peak current of axial GaSb/InAs-(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm2, while their axial counterparts at most carry Jpeak = 77 kA/cm2, normalized to the largest cross-sectional area of the nanowire.
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    34. 34
      Ganjipour, B.; Dey, A. W.; Borg, B. M.; Ek, M.; Pistol, M.-E.; Dick, K. A.; Wernersson, L.-E.; Thelander, C. High Current Density Esaki Tunnel Diodes Based on GaSb-InAsSb Heterostructure Nanowires. Nano Lett. 2011, 11 (10), 4222– 4226,  DOI: 10.1021/nl202180b
      34
      High Current Density Esaki Tunnel Diodes Based on GaSb-InAsSb Heterostructure Nanowires
      Ganjipour, Bahram; Dey, Anil W.; Borg, B. Mattias; Ek, Martin; Pistol, Mats-Erik; Dick, Kimberly A.; Wernersson, Lars-Erik; Thelander, Claes
      Nano Letters (2011), 11 (10), 4222-4226CODEN: NALEFD; ISSN:1530-6984. (American Chemical Society)
      The authors present elec. characterization of broken gap GaSb-InAsSb nanowire heterojunctions. Esaki diode characteristics with max. reverse current of 1750 kA/cm2 at 0.50 V, max. peak current of 67 kA/cm2 at 0.11 V, and peak-to-valley ratio (PVR) of 2.1 were obtained at room temp. The reverse c.d. is comparable to that of state-of-the-art tunnel diodes based on heavily doped p-n junctions. However, the GaSb-InAsSb diodes studied in this work do not rely on heavy doping, which permits studies of transport mechanisms in simple transistor structures processed with high-κ gate dielecs. and top-gates. Such processing results in devices with improved PVR (3.5) and stability of the elec. properties.
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    35. 35
      Carnevale, S. D.; Marginean, C.; Phillips, P. J.; Kent, T. F.; Sarwar, A. T. M. G.; Mills, M. J.; Myers, R. C. Coaxial Nanowire Resonant Tunneling Diodes from Non-Polar AlN/GaN on Silicon. Appl. Phys. Lett. 2012, 100 (14), 142115,  DOI: 10.1063/1.3701586
      35
      Coaxial nanowire resonant tunneling diodes from non-polar AlN/GaN on silicon
      Carnevale, S. D.; Marginean, C.; Phillips, P. J.; Kent, T. F.; Sarwar, A. T. M. G.; Mills, M. J.; Myers, R. C.
      Applied Physics Letters (2012), 100 (14), 142115/1-142115/4CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)
      Resonant tunneling diodes are formed using AlN/GaN core-shell nanowire heterostructures grown by plasma assisted MBE on n-Si(111) substrates. By a coaxial geometry, these devices take advantage of non-polar (m-plane) nanowire sidewalls. Device modeling predicts non-polar orientation should enhance resonant tunneling compared to a polar structure, and that AlN double barriers will lead to higher peak-to-valley current ratios compared to AlGaN barriers. Elec. measurements of ensembles of nanowires show neg. differential resistance appearing only at cryogenic temp. Individual nanowire measurements show neg. differential resistance at room temp. with peak c.d. of 5 × 105 A/cm2. (c) 2012 American Institute of Physics.
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    36. 36
      Nourbakhsh, A.; Zubair, A.; Dresselhaus, M. S.; Palacios, T. Transport Properties of a MoS2/WSe2 Heterojunction Transistor and Its Potential for Application. Nano Lett. 2016, 16 (2), 1359– 1366,  DOI: 10.1021/acs.nanolett.5b04791
      36
      Transport Properties of a MoS2/WSe2 Heterojunction Transistor and Its Potential for Application
      Nourbakhsh, Amirhasan; Zubair, Ahmad; Dresselhaus, Mildred S.; Palacios, Tomas
      Nano Letters (2016), 16 (2), 1359-1366CODEN: NALEFD; ISSN:1530-6984. (American Chemical Society)
      This paper studies band-to-band tunneling in the transverse and lateral directions of van der Waals MoS2/WSe2 heterojunctions. We observe room-temp. neg. differential resistance (NDR) in a heterojunction diode comprised of few-layer WSe2 stacked on multilayer MoS2. The presence of NDR is attributed to the lateral band-to-band tunneling at the edge of the MoS2/WSe2 heterojunction. The backward tunneling diode shows an av. conductance slope of 75 mV/dec with a high curvature coeff. of 62 V-1. Assocd. with the tunnel-diode characteristics, a pos.-to-neg. transconductance in the MoS2/WSe2 heterojunction transistors is obsd. The transition is induced by strong interlayer coupling between the films, which results in charge d. and energy-band modulation. The sign change in transconductance is particularly useful for multivalued logic (MVL) circuits, and we therefore propose and demonstrate for the first time an MVL-inverter that shows three levels of logic using one pair of p-type transistors.
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    37. 37
      Huang, M.; Li, S.; Zhang, Z.; Xiong, X.; Li, X.; Wu, Y. Multifunctional High-Performance van Der Waals Heterostructures. Nat. Nanotechnol. 2017, 12 (12), 1148– 1154,  DOI: 10.1038/nnano.2017.208
      37
      Multifunctional high-performance van der Waals heterostructures
      Huang, Mingqiang; Li, Shengman; Zhang, Zhenfeng; Xiong, Xiong; Li, Xuefei; Wu, Yanqing
      Nature Nanotechnology (2017), 12 (12), 1148-1154CODEN: NNAABX; ISSN:1748-3387. (Nature Research)
      A range of novel two-dimensional materials have been actively explored for More Moore and More-than-Moore device applications because of their ability to form van der Waals heterostructures with unique electronic properties. However, most of the reported electronic devices exhibit insufficient control of multifunctional operations. Here, we leverage the band-structure alignment properties of narrow-bandgap black phosphorus and large-bandgap molybdenum disulfide to realize vertical heterostructures with an ultrahigh rectifying ratio approaching 106 and on-off ratio up to 107. Furthermore, we design and fabricate tunable multivalue inverters, in which the output logic state and window of the mid-logic can be controlled by specific pairs of channel length and, most importantly, by the elec. field, which shifts the band-structure alignment across the heterojunction. Finally, high gains over 150 are achieved in the inverters with optimized device geometries, showing great potential for future logic applications.
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    38. 38
      Lv, W.; Fu, X.; Luo, X.; Lv, W.; Cai, J.; Zhang, B.; Wei, Z.; Liu, Z.; Zeng, Z. Multistate Logic Inverter Based on Black Phosphorus/SnSeS Heterostructure. Adv. Electron. Mater. 2019, 5 (1), 1800416,  DOI: 10.1002/aelm.201800416
      There is no corresponding record for this reference.
    39. 39
      Xiong, X.; Kang, J.; Hu, Q.; Gu, C.; Gao, T.; Li, X.; Wu, Y. Reconfigurable Logic-in-Memory and Multilingual Artificial Synapses Based on 2D Heterostructures. Adv. Funct. Mater. 2020, 30 (11), 1909645,  DOI: 10.1002/adfm.201909645
      39
      Reconfigurable logic-in-memory and multilingual artificial synapses based on 2D heterostructures
      Xiong, Xiong; Kang, Jiyang; Hu, Qianlan; Gu, Chengru; Gao, Tingting; Li, Xuefei; Wu, Yanqing
      Advanced Functional Materials (2020), 30 (11), 1909645CODEN: AFMDC6; ISSN:1616-301X. (Wiley-VCH Verlag GmbH & Co. KGaA)
      Nonvolatile logic devices have attracted intensive research attentions recently for energy efficiency computing, where data computing and storage can be realized in the same device structure. Various approaches have been adopted to build such devices; however, the functionality and versatility are still very limited. Here, 2-dimensional van der Waals heterostructures based on direct band gap materials black phosphorus and rhenium disulfide for the nonvolatile ternary logic operations is demonstrated for the first time with the ultrathin oxide layer from the black phosphorus serving as the charge trapping as well as band-to-band tunneling layer. Furthermore, an artificial electronic synapse based on this heterostructure is demonstrated to mimic trilingual synaptic response by changing the input base voltage. Besides, artificial neural network simulation based on the electronic synaptic arrays using the handwritten digits data sets demonstrates a high recognition accuracy of 91.3%. This work provides a path toward realizing multifunctional nonvolatile logic-in-memory applications based on novel 2D heterostructures.
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    40. 40
      Dong, J.; Liu, F.; Wang, F.; Wang, J.; Li, M.; Wen, Y.; Wang, L.; Wang, G.; He, J.; Jiang, C. Configuration-Dependent Anti-Ambipolar van Der Waals p–n Heterostructures Based on Pentacene Single Crystal and MoS2. Nanoscale 2017, 9 (22), 7519– 7525,  DOI: 10.1039/C7NR01822C
      40
      Configuration-dependent anti-ambipolar van der Waals p-n heterostructures based on pentacene single crystal and MoS2
      Dong, Ji; Liu, Fengjing; Wang, Feng; Wang, Jiawei; Li, Molin; Wen, Yao; Wang, Liang; Wang, Gongtang; He, Jun; Jiang, Chao
      Nanoscale (2017), 9 (22), 7519-7525CODEN: NANOHL; ISSN:2040-3372. (Royal Society of Chemistry)
      Recently, van der Waals heterostructures (vdWHs) have trigged intensive interest due to their novel electronic and optoelectronic properties. The vdWHs could be achieved by stacking two dimensional layered materials (2DLMs) on top of another and vertically kept by van der Waals forces. Furthermore, org. semiconductors are also known to interact via van der Waals forces, which offer an alternative for the fabrication of org.-inorg. p-n vdWHs. However, the performances of org.-inorg. p-n vdWHs produced so far are rather poor, owing to the unmatched elec. property between the 2DLMs and org. polycryst. films. To make improvements in such novel heterostructure architectures, here we adopt high quality org. single crystals instead of polycryst. films to construct a pentacene/MoS2 p-n vdWH. The vdWHs show a much higher c.d. and better anti-ambipolar characteristics with a highest transconductance of 211 nS. Moreover, device configuration-dependent transfer characteristics are demonstrated and a mechanism of a gate bias modulated vertical space charge zone existing at the vertical p-n vdWHs interface is proposed. These findings provide a new route to optimize the org.-inorg. p-n vdWHs and a guideline for studying the intrinsic properties of vdWHs.
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    41. 41
      Li, S.; Chen, X.; Liu, L.; Zeng, Z.; Chang, S.; Wang, H.; Wu, H.; Long, S.; Liu, C. Micron Channel Length ZnO Thin Film Transistors Using Bilayer Electrodes. J. Colloid Interface Sci. 2022, 622, 769– 779,  DOI: 10.1016/j.jcis.2022.04.016
      41
      Micron channel length ZnO thin film transistors using bilayer electrodes
      Li, Sizhe; Chen, Xue; Liu, Li; Zeng, Zhiyu; Chang, Sheng; Wang, Hao; Wu, Hao; Long, Shibing; Liu, Chang
      Journal of Colloid and Interface Science (2022), 622 (), 769-779CODEN: JCISA5; ISSN:0021-9797. (Elsevier B.V.)
      Micro light-emitting diodes (Micro-LEDs) are currently attracting more and more attention. Thin film transistors (TFTs) with micron channel lengths can be used to drive Micro-LEDs. The key parameters of TFTs, such as mobility, ION/IOFF and threshold voltage, still need to be improved. In this study, we propose and exptl. demonstrate ZnO TFTs using bilayer electrodes to overcome the short channel effects when the channel length is scaled down to 3μm. Ti, Mo and Sn interlayers not only serve as diffusion barriers to prohibit migration of Cu atoms from the top electrodes, but also enhance adhesive energy of the metal electrodes on ZnO channel layers. ZnO TFTs using Cu/Ti bilayer electrodes exhibit the best performance, e.g., a high mobility of 45.3 cm2V-1s-1, a high ION/IOFF ratio of 4.28 x 109, a low subthreshold of 0.24 V/dec and a proper threshold voltage of 1.13 V. The high mobility can be attributed to a significant decrease of the barrier height and a slight narrowing of the space charge layer, and the high ratio of ION/IOFF is concerned with the high electron concn. under an ON-state condition. Thus, ZnO TFTs using Cu/Ti bilayer electrodes can be used in next-generation displays.
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    42. 42
      Li, H.; Han, D.; Dong, J.; Yi, Z.; Zhou, X.; Zhang, S.; Zhang, X.; Wang, Y. Enhanced Performance of Atomic Layer Deposited Thin-Film Transistors With High-Quality ZnO/Al2O3 Interface. IEEE Trans. Electron Devices 2020, 67 (2), 518– 523,  DOI: 10.1109/TED.2019.2957048
      42
      Enhanced performance of atomic layer deposited thin-film transistors with high-quality ZnO/Al2O3 interface
      Li, Huijin; Han, Dedong; Dong, Junchen; Yi, Zhuang; Zhou, Xiaobin; Zhang, Shengdong; Zhang, Xing; Wang, Yi
      IEEE Transactions on Electron Devices (2020), 67 (2), 518-523CODEN: IETDAI; ISSN:1557-9646. (Institute of Electrical and Electronics Engineers)
      We fabricated ZnO channel/Al2O3 gate dielec. thin-film transistors (TFTs) by at. layer deposition (ALD) continuous growth process. The effects of the channel and the dielec. continuous growth on the performance of TFTs were investigated. Compared with noncontinuous growth ZnO/Al2O3 films, continuous growth ZnO/Al2O3 films with no obvious buffer layer and less residual O-H bonds possess superior ZnO/Al2O3 interface quality. The continuous growth TFTs exhibit a field-effect mobility of 19.6 cm2 V-1s-1, a subthreshold swing of 0.13 V dec-1, a high ION/IOFF of 4.1 x 109, a hysteresis window of 0.09 V, and an excellent uniformity of elec. characteristics. Continuous growth TFTs also demonstrate better stability with minor shifts of Vth 0.6 V [pos. bias stress (PBS)] and Vth - 0.3 V [neg. bias stress (NBS)]. The faster falling rates of activation energy for continuous growth TFTs indicate that the total trap d. is reduced through the continuous growth of active layer and dielec. layer. Our results suggest that the ALD-based continuous growth process could enhance the performance of TFTs.
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    43. 43
      Acharya, R.; Günder, D.; Breuer, T.; Schmitz, G.; Klauk, H.; Witte, G. Stability of Organic Thin-Film Transistors Based on Ultrathin Films of Dinaphtho[2,3-b:2′,3′-f]Thieno[3,2- b]Thiophene (DNTT). Journal of Materials Chemistry C 2021, 9 (1), 270– 280,  DOI: 10.1039/D0TC04554C
      43
      Stability of organic thin-film transistors based on ultrathin films of dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT)
      Acharya, Rachana; Guender, Darius; Breuer, Tobias; Schmitz, Guido; Klauk, Hagen; Witte, Gregor
      Journal of Materials Chemistry C: Materials for Optical and Electronic Devices (2021), 9 (1), 270-280CODEN: JMCCCX; ISSN:2050-7534. (Royal Society of Chemistry)
      Org. thin-film transistors (TFTs) based on ultrathin semiconductor films are potentially useful as highly sensitive phys., chem. or biol. sensors and may also help in the development of a better understanding of the relations between structural and charge-transport characteristics of thin films of org. semiconductors. A particularly promising small-mol. org. semiconductor is dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT). However, it was recently reported that ultrathin DNTT films spontaneously undergo dramatic morphol. changes within minutes after deposition that lead to the disaggregation of the initially closed (or at least connected) single-monolayer films into disconnected multilayer islands. Here, we investigate how this spontaneous structural reconfiguration affects the characteristics of TFTs based on ultrathin DNTT films and explore the extent to which it can be prevented by cryogenic cooling or in situ encapsulation. We fabricated inverted coplanar TFTs with a hybrid aluminum oxide/alkylphosphonic acid self-assembled monolayer gate dielec. and vacuum-deposited DNTT films with nominal thicknesses of 2.5 or 25 nm. Using at. force microscopy (AFM) we monitored the spontaneous changes in the DNTT morphol. in a quasi-continuous manner over a period of 12 h after deposition. The charge-carrier mobility of the ultrathin DNTT TFTs was found to decrease rapidly, while the mobility of the TFTs with the thicker DNTT films is far more stable. We also found that the initial closed-monolayer morphol. of the ultrathin DNTT films is preserved when the substrates are cooled to cryogenic temps. immediately after the DNTT deposition, but that the morphol. changes resume upon returning the substrates to room temp. Furthermore, we fabricated TFTs in which the ultrathin DNTT films were encapsulated in situ with a vacuum-deposited film of polytetrafluoroethylene, C60 or titanyl phthalocyanine immediately following the DNTT deposition and found that the encapsulation decelerates the structural reorganization of the ultrathin DNTT films and the concurrent degrdn. of the carrier mobility.
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    44. 44
      Ibrahim, G. H.; Zschieschang, U.; Klauk, H.; Reindl, L. High-Frequency Rectifiers Based on Organic Thin-Film Transistors on Flexible Substrates. IEEE Trans. Electron Devices 2020, 67 (6), 2365– 2371,  DOI: 10.1109/TED.2020.2989730
      44
      High-frequency rectifiers based on organic thin-film transistors on flexible substrates
      Ibrahim, Ghada H.; Zschieschang, Ute; Klauk, Hagen; Reindl, Leonhard
      IEEE Transactions on Electron Devices (2020), 67 (6), 2365-2371CODEN: IETDAI; ISSN:1557-9646. (Institute of Electrical and Electronics Engineers)
      Rectifier circuits featuring low threshold voltages and high cutoff frequencies based on p-channel org. thin-film transistors (TFTs) have been designed, fabricated and characterized. The TFTs and circuits were fabricated by shadow-mask lithog. on flexible plastic substrates using the vacuum-deposited small-mol. org. semiconductor dinaphtho[2,3-b:2',3'-f]thieno[3,2-b] thiophene (DNTT). The TFTs have a gate dielec. with a thickness of 5.3 nm and a channel length of 10μm. The study considers the frequency characteristics of diode-connected transistors (transdiodes) and adopts circuit techniques from silicon CMOS technol., namely single-stage and multistage dynamic-threshold-compensated differential rectifiers. The characterization of the rectifier circuits indicates cutoff frequencies up to 4.75 MHz at a peak-to-peak input voltage of 3 V for transdiodes, up to 32 MHz at a peak-to-peak input voltage of 1.5 V for single-stage differential rectifiers and up to 7.5 MHz at a peak-to-peak input voltage of 1.5 V for two-stage rectifiers. The efficiency is 25% for a load of 10 MΩ and below 1% for a load of 1 MΩ.
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    45. 45
      Kobashi, K.; Hayakawa, R.; Chikyow, T.; Wakayama, Y. Negative Differential Resistance Transistor with Organic P-n Heterojunction. Adv. Electron. Mater. 2017, 3 (8), 1700106,  DOI: 10.1002/aelm.201700106
      There is no corresponding record for this reference.
    46. 46
      On, S.; Kim, Y.-J.; Lee, H.-K.; Yoo, H. Ambipolar and Anti-Ambipolar Thin-Film Transistors from Edge-on Small-Molecule Heterostructures. Appl. Surf. Sci. 2021, 542, 148616,  DOI: 10.1016/j.apsusc.2020.148616
      46
      Ambipolar and anti-ambipolar thin-film transistors from edge-on small-molecule heterostructures
      On, Sungmin; Kim, Young-Joon; Lee, Han-Koo; Yoo, Hocheon
      Applied Surface Science (2021), 542 (), 148616CODEN: ASUSEE; ISSN:0169-4332. (Elsevier B.V.)
      Heterostructure electronic devices potentially provide opportunities for novel transistor operations, including ambipolar and anti-ambipolar switching characteristics. However, there are still no previous studies investigating the phys., chem., and morphol. properties of small-mol. semiconductor films deposited as heterojunctions. Here, we systemically investigate chem. and morphol. structure in a heterostructure of small-mol. org. semiconductors using XPS, near-edge X-ray absorption of fine structure (NEXAFS), and UPS (UPS). The anal. reveals that dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) and N,N'-ditridecylperylenediimide (PTCDI-C13) maintain their chem. compns., energy structure, and edge-on mol. orientations (tilt angle = 66°). Furthermore, ambipolar and anti-ambipolar transistors are demonstrated using the edge-on DNTT/PTCDI-C13 heterostructure. These transistors enable CMOS-like inverter and ternary inverter operations as resp. example applications of ambipolar and anti-ambipolar transistors.
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    47. 47
      Nakata, M.; Tsuji, H.; Sato, H.; Nakajima, Y.; Fujisaki, Y.; Takei, T.; Yamamoto, T.; Fujikake, H. Influence of Oxide Semiconductor Thickness on TFT Characteristics. 2012 19th International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD) ; 2012.
      There is no corresponding record for this reference.
    48. 48
      Chang, J.-F.; Shie, H.-S.; Yang, Y.-W.; Wang, C.-H. Study on Correlation between Structural and Electronic Properties of Fluorinated Oligothiophenes Transistors by Controlling Film Thickness. Crystals 2019, 9 (3), 144,  DOI: 10.3390/cryst9030144
      48
      Study on correlation between structural and electronic properties of fluorinated oligothiophenes transistors by controlling film thickness
      Chang, Jui-Fen; Shie, Hua-Shiuan; Yang, Yaw-Wen; Wang, Chia-Hsin
      Crystals (2019), 9 (3), 144/1-144/14CODEN: CRYSBC; ISSN:2073-4352. (MDPI AG)
      α,ω-Diperfluorohexylquaterthiophene (DFH-4T) has been an attractive n-type material employed in the development of high-mobility org. field-effect transistors. This paper presents a systematic study of the relationship between DFH-4T transistor performance and film structure properties as controlled by deposited thickness. When the DFH-4T thickness increases from 8 nm to 80 nm, the room-temp. field-effect mobility increases monotonically from 0.01 to 1 cm2·V-1·s-1, while the threshold voltage shows a different trend of first decrease then increase. The morphol. of thin films revealed by at. force microscopy shows a dramatic change from multilayered terrace to stacked rod like structures as the film thickness is increased. Yet the crystallite structure and the orientation of mol. constituent, as detd. by X-ray diffraction and near-edge X-ray absorption fine structure resp., do not differ much with respect to film thickness increase. Further analyses of low-temp. transport measurements with mobility-edge model demonstrate that the electronic states of DFH-4T transistors are mainly detd. by the film continuity and crystallinity of the bottom multilayered terrace. Moreover, the capacitance-voltage measurements of DFH-4T metal-insulator-semiconductor diodes demonstrate a morphol. dependence of charge injection from top contacts, which well explains the variation of threshold voltage with thickness. The overall study provides a deeper understanding of microstructural and mol. growth of DFH-4T film and clarify the structural effects on charge transport and injection for implementation of high-mobility top-contact transistors.
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      Lovie, P. Coefficient of Variation. Encyclopedia of Statistics in Behavioral Science; John Wiley & Sons, Ltd.: Chichester, 2005; Vol. 1, pp 317– 318, DOI: 10.1002/0470013192.bsa107 .
      There is no corresponding record for this reference.
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      Stanford University CNTFET Model, https://nano.stanford.edu/downloads/stanford-cnfet-model (accessed Feb 14, 2022).
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      Predictive Technology Model (PTM), http://ptm.asu.edu (accessed Feb 14, 2022).
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      Etiemble, D. Comparing Ternary and Binary Adders and Multipliers. 2019, arXiv:1908.07299, https://arxiv.org/abs/1908.07299 (accessed Feb 8, 2022).
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    53. 53
      Lee, S.; Striakhilev, D.; Jeon, S.; Nathan, A. Unified Analytic Model for Current–Voltage Behavior in Amorphous Oxide Semiconductor TFTs. IEEE Electron Device Lett. 2014, 35 (1), 84– 86,  DOI: 10.1109/LED.2013.2290532
      53
      Unified analytic model for current-voltage behavior in amorphous oxide semiconductor TFTs
      Lee, Sungsik; Striakhilev, Denis; Jeon, Sanghun; Nathan, Arokia
      IEEE Electron Device Letters (2014), 35 (1), 84-86CODEN: EDLEDZ; ISSN:0741-3106. (Institute of Electrical and Electronics Engineers)
      We present a simple and semi-phys. anal. description of the current-voltage characteristics of amorphous oxide semiconductor thin-film transistors in the above-threshold and sub-threshold regions. Both regions are described by single unified expression that employs the same set of model parameter values directly extd. from measured terminal characteristics. The model accurately reproduces measured characteristics of amorphous semiconductor thin film transistors in general, yielding a scatter of <4%.
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  • Supporting Information

    Supporting Information

    The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsnano.2c03523.

    • Fabrication process flow of the ZnO–DNTT AAS device, XPS analysis of ZnO and DNTT, transfer curves and transconductance of ZnO–DNTT AAS device dependence on voltage bias, transfer curves of ZnO and DNTT single TFT dependence on channel thickness and doping type, various STI schemes, comparison of STI operation, various ternary circuit designs and their operation (Figures S1–S9) and PM ternary device switching table (Table S1) (PDF)


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