Demonstration of Anti-ambipolar Switch and Its Applications for Extremely Low Power Ternary Logic CircuitsClick to copy article linkArticle link copied!
- Yongsu LeeYongsu LeeCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of KoreaMore by Yongsu Lee
- Sunmean KimSunmean KimCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of KoreaMore by Sunmean Kim
- Ho-In LeeHo-In LeeCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of KoreaMore by Ho-In Lee
- Seung-Mo KimSeung-Mo KimCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of KoreaMore by Seung-Mo Kim
- So-Young KimSo-Young KimCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of KoreaMore by So-Young Kim
- Kiyung KimKiyung KimCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of KoreaMore by Kiyung Kim
- Heejin KwonHeejin KwonCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of KoreaMore by Heejin Kwon
- Hae-Won LeeHae-Won LeeCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of KoreaMore by Hae-Won Lee
- Hyeon Jun HwangHyeon Jun HwangCenter for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of KoreaMore by Hyeon Jun Hwang
- Seokhyeong Kang*Seokhyeong Kang*E-mail: [email protected]Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of KoreaMore by Seokhyeong Kang
- Byoung Hun Lee*Byoung Hun Lee*E-mail: [email protected]Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-ro 77, Nam-gu, Pohang, Gyeongbuk 37673, Republic of KoreaMore by Byoung Hun Lee
Abstract
Anti-ambipolar switch (AAS) devices at a narrow bias region are necessary to solve the intrinsic leakage current problem of ternary logic circuits. In this study, an AAS device with a very high peak-to-valley ratio (∼106) and adjustable operating range characteristics was successfully demonstrated using a ZnO and dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene heterojunction structure. The entire device integration was completed at a low thermal budget of less than 200 °C, which makes this AAS device compatible with monolithic 3D integration. A 1-trit ternary full adder designed with this AAS device exhibits excellent power–delay product performance (∼122 aJ) with extremely low power (∼0.15 μW, 7 times lower than the reference circuit) and lower device count than those of other ternary device candidates.
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License Summary*
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License Summary*
You are free to share(copy and redistribute) this article in any medium or format and to adapt(remix, transform, and build upon) the material for any purpose, even commercially within the parameters below:
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Results and Discussion
device | JD [nA/μm] | PVR | fab. method | fab. T [°C] | EOT [nm] | |VD| [V] |
---|---|---|---|---|---|---|
ZnO–DNTT (this work) | 0.9–5.6 | 105–106 | ALD and evaporation | 120 | 90 | 5–30 |
Si (p+–i–n+) (29) | 0.004–2 | 2–10 | CMOS | 25 | 0.05–0.7 | |
Si (n+–p+–n+) (30) | 3.6 | 2 | CMOS | 2 | 0.001 | |
Si (p+–n+–p+) (31) | 20–109 | 1–5.5 | CMOS | 800 | 3 | 0.01–0.05 |
Si–Ge nanowire (32) | 0.22–270 | 20–48 | CVD | 495 | 2 | 0.2–0.8 |
GaSb–InAsSb nanowire (33) | 2200 | 1.6 | epitaxy | 500 | 10 | 0.5 |
MoS2–WSe2 (36) | 30 | 103 | exfoliation | 360 | >300 | 1 |
SnSeS–BP (37) | 133 | 102 | exfoliation | 4.68 | 1 | |
MoS2–BP (38) | 67 | 103 | exfoliation | 250 | 300 | 1 |
ReS2–BP (39) | 4000 | 105 | exfoliation | 250 | 3.9 | 1 |
MoS2–pentacene (40) | 450 | 103 | exfoliation | 100 | 300 | 10 |
PTCDI-C8-6T (45) | 0.2 | 5 × 104 | evaporation | 120 | >200 | 60 |
PTCDI-C8–DNTT (46) | 0.05–0.6 | 103–105 | evaporation | 175 | >350 | 30–60 |
logic architecture | VDD [V] | # Tr | power [μW] | delay [ps] | PDP [aJ] | |
---|---|---|---|---|---|---|
1-trit ternary | this work (L = W = 100 nm) | 2 | 88 | 0.15 | 799 | 122 |
CNTFET (L = 100 nm) | 1 | 110 | 1.07 | 160 | 172 | |
2-bits binary | 90 nm CMOS | 2 | 56 | 7.15 | 120 | 858 |
1 | 56 | 0.096 | 200 | 19 |
Conclusion
Methods
Fabrication Process and Electrical Characterization of ZnO–DNTT AAS Device
Device and Logic Circuit Modeling
Supporting Information
The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsnano.2c03523.
Fabrication process flow of the ZnO–DNTT AAS device, XPS analysis of ZnO and DNTT, transfer curves and transconductance of ZnO–DNTT AAS device dependence on voltage bias, transfer curves of ZnO and DNTT single TFT dependence on channel thickness and doping type, various STI schemes, comparison of STI operation, various ternary circuit designs and their operation (Figures S1–S9) and PM ternary device switching table (Table S1) (PDF)
Terms & Conditions
Most electronic Supporting Information files are available without a subscription to ACS Web Editions. Such files may be downloaded by article for research use (if there is a public use license linked to the relevant article, that license may permit other uses). Permission may be obtained from ACS for other uses through requests via the RightsLink permission system: http://pubs.acs.org/page/copyright/permissions.html.
Acknowledgments
This work was partially supported by Creative Materials Discovery Program on Creative Multilevel Research Center (2017M3D1A1040834) and FEOL platform development program (2020M3F3A2A02082436) through the National Research Foundation of Korea (NRF), funded by the Ministry of Science and ICT, Korea.
References
This article references 53 other publications.
- 1Moore, G. E. Cramming More Components onto Integrated Circuits. Proc. IEEE 1998, 86 (1), 4, DOI: 10.1109/JPROC.1998.658762Google ScholarThere is no corresponding record for this reference.
- 2Hiramoto, T. Five Nanometre CMOS Technology. Nat. Electron 2019, 2 (12), 557– 558, DOI: 10.1038/s41928-019-0343-xGoogle ScholarThere is no corresponding record for this reference.
- 3Khan, H. N.; Hounshell, D. A.; Fuchs, E. R. H. Science and Research Policy at the End of Moore’s Law. Nat. Electron 2018, 1 (1), 14– 21, DOI: 10.1038/s41928-017-0005-9Google ScholarThere is no corresponding record for this reference.
- 4Salahuddin, S.; Ni, K.; Datta, S. The Era of Hyper-Scaling in Electronics. Nat. Electron 2018, 1 (8), 442– 450, DOI: 10.1038/s41928-018-0117-xGoogle ScholarThere is no corresponding record for this reference.
- 5Akinwande, D.; Huyghebaert, C.; Wang, C.-H.; Serna, M. I.; Goossens, S.; Li, L.-J.; Wong, H.-S. P.; Koppens, F. H. L. Graphene and Two-Dimensional Materials for Silicon Technology. Nature 2019, 573 (7775), 507– 518, DOI: 10.1038/s41586-019-1573-9Google Scholar5https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC1MXhvVCmu73F&md5=458f9a3e7f71f5718f0bd150c54bdb2dGraphene and two-dimensional materials for silicon technologyAkinwande, Deji; Huyghebaert, Cedric; Wang, Ching-Hua; Serna, Martha I.; Goossens, Stijn; Li, Lain-Jong; Wong, H.-S. Philip; Koppens, Frank H. L.Nature (London, United Kingdom) (2019), 573 (7775), 507-518CODEN: NATUAS; ISSN:0028-0836. (Nature Research)The development of silicon semiconductor technol. has produced breakthroughs in electronics-from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones-by downscaling the phys. size of devices and wires to the nanometer regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device performance at the at. limit, and a synergistic combination of 2D materials with silicon chips promises a heterogeneous platform to deliver massively enhanced potential based on silicon technol. Integration is achieved via three-dimensional monolithic construction of multifunctional high-rise 2D silicon chips, enabling enhanced performance by exploiting the vertical direction and the functional diversification of the silicon platform for applications in opto-electronics and sensing. Here we review the opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems, and also consider the prospects for computational and non-computational applications.
- 6Son, Y.; Frost, B.; Zhao, Y.; Peterson, R. L. Monolithic Integration of High-Voltage Thin-Film Electronics on Low-Voltage Integrated Circuits Using a Solution Process. Nat. Electron 2019, 2 (11), 540– 548, DOI: 10.1038/s41928-019-0316-0Google Scholar6https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC1MXitFOltb7N&md5=b0c680377630015e231dc722a49cf767Monolithic integration of high-voltage thin-film electronics on low-voltage integrated circuits using a solution processSon, Youngbae; Frost, Brad; Zhao, Yunkai; Peterson, Rebecca L.Nature Electronics (2019), 2 (11), 540-548CODEN: NEALB3; ISSN:2520-1131. (Nature Research)The performance of silicon complementary metal-oxide-semiconductor integrated circuits can be enhanced through the monolithic three-dimensional integration of addnl. device layers. For example, silicon integrated circuits operate at low voltages (around 1 V) and high-voltage handling capabilities could be provided by monolithically integrating thin-film transistors. Here we show that high-voltage amorphous oxide semiconductor thin-film transistors can be integrated on top of a silicon integrated circuit contg. 100-nm-node fin field-effect transistors using an in-air soln. process. To solve the problem of voltage mismatch between these two device layers, we use a top Schottky, bottom ohmic contact structure to reduce the amorphous oxide semiconductor circuit switching voltage. These contacts are used to form Schottky-gated thin-film transistors and vertical thin-film diodes with excellent switching performance. As a result, we can create high-voltage amorphous oxide semiconductor circuits with switching voltages less than 1.2 V that can be directly integrated with silicon integrated circuits.
- 7Choi, J.; Han, J. S.; Hong, K.; Kim, S. Y.; Jang, H. W. Organic–Inorganic Hybrid Halide Perovskites for Memories, Transistors, and Artificial Synapses. Adv. Mater. 2018, 30 (42), 1704002, DOI: 10.1002/adma.201704002Google ScholarThere is no corresponding record for this reference.
- 8Andrae, A. S. G.; Edler, T. On Global Electricity Usage of Communication Technology: Trends to 2030. Challenges 2015, 6 (1), 117– 157, DOI: 10.3390/challe6010117Google ScholarThere is no corresponding record for this reference.
- 9Shibata, T.; Ohmi, T. A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations. IEEE Trans. Electron Devices 1992, 39 (6), 1444– 1455, DOI: 10.1109/16.137325Google ScholarThere is no corresponding record for this reference.
- 10Rine, D. C. Computer Science and Multiple-Valued Logic: Theory and Applications; Elsevier: Amsterdam, 1977.Google ScholarThere is no corresponding record for this reference.
- 11Gaudet, V. A Survey and Tutorial on Contemporary Aspects of Multiple-Valued Logic and Its Application to Microelectronic Circuits. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2016, 6 (1), 5– 12, DOI: 10.1109/JETCAS.2016.2528041Google ScholarThere is no corresponding record for this reference.
- 12Smith The Prospects for Multivalued Logic: A Technology and Applications View. IEEE Transactions on Computers 1981, C–30 (9), 619– 634, DOI: 10.1109/TC.1981.1675860Google ScholarThere is no corresponding record for this reference.
- 13Chen, W.-H.; Dou, C.; Li, K.-X.; Lin, W.-Y.; Li, P.-Y.; Huang, J.-H.; Wang, J.-H.; Wei, W.-C.; Xue, C.-X.; Chiu, Y.-C.; King, Y.-C.; Lin, C.-J.; Liu, R.-S.; Hsieh, C.-C.; Tang, K.-T.; Yang, J. J.; Ho, M.-S.; Chang, M.-F. CMOS-Integrated Memristive Non-Volatile Computing-in-Memory for AI Edge Processors. Nat. Electron 2019, 2 (9), 420– 428, DOI: 10.1038/s41928-019-0288-0Google Scholar13https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC1MXhs1Gisr3K&md5=7b4b668979e49a7839eb7632750a244fCMOS-integrated memristive non-volatile computing-in-memory for AI edge processorsChen, Wei-Hao; Dou, Chunmeng; Li, Kai-Xiang; Lin, Wei-Yu; Li, Pin-Yi; Huang, Jian-Hao; Wang, Jing-Hong; Wei, Wei-Chen; Xue, Cheng-Xin; Chiu, Yen-Cheng; King, Ya-Chin; Lin, Chorng-Jung; Liu, Ren-Shuo; Hsieh, Chih-Cheng; Tang, Kea-Tiong; Yang, J. Joshua; Ho, Mon-Shu; Chang, Meng-FanNature Electronics (2019), 2 (9), 420-428CODEN: NEALB3; ISSN:2520-1131. (Nature Research)Non-volatile computing-in-memory (nvCIM) could improve the energy efficiency of edge devices for artificial intelligence applications. The basic functionality of nvCIM has recently been demonstrated using small-capacity memristor crossbar arrays combined with peripheral readout circuits made from discrete components. However, the advantages of the approach in terms of energy efficiency and operating speeds, as well as its robustness against device variability and sneak currents, have yet to be demonstrated exptl. Here, we report a fully integrated memristive nvCIM structure that offers high energy efficiency and low latency for Boolean logic and multiply-and-accumulation (MAC) operations. We fabricate a 1 Mb resistive random-access memory (ReRAM) nvCIM macro that integrates a one-transistor-one-resistor ReRAM array with control and readout circuits on the same chip using an established 65 nm foundry complementary metal-oxide-semiconductor (CMOS) process. The approach offers an access time of 4.9 ns for three-input Boolean logic operations, a MAC computing time of 14.8 ns and an energy efficiency of 16.95 tera operations per s per W. Applied to a deep neural network using a split binary-input ternary-weighted model, the system can achieve an inference accuracy of 98.8% on the MNIST dataset.
- 14Yang, R.; Li, H.; Smithe, K. K. H.; Kim, T. R.; Okabe, K.; Pop, E.; Fan, J. A.; Wong, H.-S. P. Ternary Content-Addressable Memory with MoS2 Transistors for Massively Parallel Data Search. Nat. Electron 2019, 2 (3), 108– 114, DOI: 10.1038/s41928-019-0220-7Google ScholarThere is no corresponding record for this reference.
- 15Kim, K.; Kim, S.; Lee, Y.; Kim, D.; Kim, S.-Y.; Kang, S.; Lee, B. H. Extreme Low Power Technology Using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction. In 2020 IEEE 50th International Symposium on Multiple-Valued Logic (ISMVL) ; 2020; pp 155– 158, DOI: 10.1109/ISMVL49045.2020.00-13 .Google ScholarThere is no corresponding record for this reference.
- 16Kim, Y. J.; Kim, S.-Y.; Noh, J.; Shim, C. H.; Jung, U.; Lee, S. K.; Chang, K. E.; Cho, C.; Lee, B. H. Demonstration of Complementary Ternary Graphene Field-Effect Transistors. Sci. Rep 2016, 6 (1), 39353, DOI: 10.1038/srep39353Google Scholar16https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC28XitFGjtLnM&md5=9c2ec2bd568c4d429fe1274d6dacca9cDemonstration of Complementary Ternary Graphene Field-Effect TransistorsKim, Yun Ji; Kim, So-Young; Noh, Jinwoo; Shim, Chang Hoo; Jung, Ukjin; Lee, Sang Kyung; Chang, Kyoung Eun; Cho, Chunhum; Lee, Byoung HunScientific Reports (2016), 6 (), 39353CODEN: SRCEC3; ISSN:2045-2322. (Nature Publishing Group)Strong demand for power redn. in state-of-the-art semiconductor devices calls for novel devices and architectures. Since ternary logic architecture can perform the same function as binary logic architecture with a much lower device d. and higher information d., a switch device suitable for the ternary logic has been pursued for several decades. However, a single device that satisfies all the requirements for ternary logic architecture has not been demonstrated. We demonstrated a ternary graphene field-effect transistor (TGFET), showing three discrete current states in one device. The ternary function was achieved by introducing a metal strip to the middle of graphene channel, which created an N-P-N or P-N-P doping pattern depending on the work function of the metal. In addn., a std. ternary inverter working at room temp. has been achieved by modulating the work function of the metal in a graphene channel. The feasibility of a ternary inverter indicates that a general ternary logic architecture can be realized using complementary TGFETs. This breakthrough will provide a key stepping-stone for an extreme-low-power computing technol.
- 17Raychowdhury, A.; Roy, K. Carbon-Nanotube-Based Voltage-Mode Multiple-Valued Logic Design. IEEE Transactions on Nanotechnology 2005, 4 (2), 168– 179, DOI: 10.1109/TNANO.2004.842068Google ScholarThere is no corresponding record for this reference.
- 18Lin, S.; Kim, Y.-B.; Lombardi, F. CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits. IEEE Transactions on Nanotechnology 2011, 10 (2), 217– 225, DOI: 10.1109/TNANO.2009.2036845Google ScholarThere is no corresponding record for this reference.
- 19Kim, S.; Lim, T.; Kang, S. An Optimal Gate Design for the Synthesis of Ternary Logic Circuits. In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) ; 2018; pp 476– 481, DOI: 10.1109/ASPDAC.2018.8297369 .Google ScholarThere is no corresponding record for this reference.
- 20Karmakar, S.; Chandy, J. A.; Jain, F. C. Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2013, 21 (5), 793– 806, DOI: 10.1109/TVLSI.2012.2198248Google ScholarThere is no corresponding record for this reference.
- 21Heo, S.; Kim, S.; Kim, K.; Lee, H.; Kim, S.-Y.; Kim, Y. J.; Kim, S. M.; Lee, H.-I.; Lee, S.; Kim, K. R.; Kang, S.; Lee, B. H. Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors. IEEE Electron Device Lett. 2018, 39 (12), 1948– 1951, DOI: 10.1109/LED.2018.2874055Google Scholar21https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC1MXhtFWhtr3N&md5=95e1cddf5208bc5fb34d23858c1023eaTernary full adder using multi-threshold voltage graphene barristorsHeo, Sunwoo; Kim, Sunmean; Kim, Kiyung; Lee, Hyeji; Kim, So-Young; Kim, Yun Ji; Kim, Seung Mo; Lee, Ho-In; Lee, Segi; Kim, Kyung Rok; Kang, Seokhyeong; Lee, Byoung HunIEEE Electron Device Letters (2018), 39 (12), 1948-1951CODEN: EDLEDZ; ISSN:1558-0563. (Institute of Electrical and Electronics Engineers)Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ∼10-16 J, which is comparable to the binary equiv. circuit. The ternary full adder was modeled using device parameters extd. from the exptl. demonstrated multi-Vth ternary graphene barristors.
- 22Kim, S.-Y.; Heo, S.; Kim, K.; Son, M.; Kim, S.-M.; Lee, H.-I.; Lee, Y.; Hwang, H. J.; Ham, M.-H.; Lee, B. H. Demonstration of Ternary Devices and Circuits Using Dual Channel Graphene Barristors. In 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL); IEEE: Fredericton, NB, Canada, 2019; pp 25– 30, DOI: 10.1109/ISMVL.2019.00013 .Google ScholarThere is no corresponding record for this reference.
- 23Lee, Y.; Kim, S.-M.; KIM, K.; Kim, S.-Y.; Lee, H.-I.; Kwon, H.; Lee, H.-W.; Kim, C.; Some, S.; Hwang, H. J.; Lee, B. H. Dual-Channel P-Type Ternary DNTT–Graphene Barristor. Submitted to Sci. Rep. 2022.Google ScholarThere is no corresponding record for this reference.
- 24Lee, L.; Hwang, J.; Jung, J. W.; Kim, J.; Lee, H.-I.; Heo, S.; Yoon, M.; Choi, S.; Van Long, N.; Park, J.; Jeong, J. W.; Kim, J.; Kim, K. R.; Kim, D. H.; Im, S.; Lee, B. H.; Cho, K.; Sung, M. M. ZnO Composite Nanolayer with Mobility Edge Quantization for Multi-Value Logic Transistors. Nat. Commun. 2019, 10 (1), 1998, DOI: 10.1038/s41467-019-09998-xGoogle Scholar24https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A280%3ADC%252BB3M7gvFerug%253D%253D&md5=67e9f17c4e388b98aa5e5ed2529dcb49ZnO composite nanolayer with mobility edge quantization for multi-value logic transistorsLee Lynn; Jung Jin Won; Kim Jongchan; Van Long Nguyen; Park Jinseon; Sung Myung Mo; Hwang Jeongwoon; Kim Jiyoung; Cho Kyeongjae; Hwang Jeongwoon; Lee Ho-In; Heo Sunwoo; Lee Byoung Hun; Yoon Minho; Im Seongil; Choi Sungju; Kim Dae Hwan; Jeong Jae Won; Kim Kyung RokNature communications (2019), 10 (1), 1998 ISSN:.A quantum confined transport based on a zinc oxide composite nanolayer that has conducting states with mobility edge quantization is proposed and was applied to develop multi-value logic transistors with stable intermediate states. A composite nanolayer with zinc oxide quantum dots embedded in amorphous zinc oxide domains generated quantized conducting states at the mobility edge, which we refer to as "mobility edge quantization". The unique quantized conducting state effectively restricted the occupied number of carriers due to its low density of states, which enable current saturation. Multi-value logic transistors were realized by applying a hybrid superlattice consisting of zinc oxide composite nanolayers and organic barriers as channels in the transistor. The superlattice channels produced multiple states due to current saturation of the quantized conducting state in the composite nanolayers. Our multi-value transistors exhibited excellent performance characteristics, stable and reliable operation with no current fluctuation, and adjustable multi-level states.
- 25Kim, S.; Kim, K.; Kim, A. R.; Lee, H.; Lee, Y.; Kim, S.; Yu, S. H.; Lee, H.; Hwang, H. J.; Sung, M. M.; Lee, B. H. Operation Principles of ZnO/Al2O3-AlDMP/ZnO Stacked-Channel Ternary Thin-Film Transistor. Adv. Electron. Mater. 2021, 7 (6), 2100247, DOI: 10.1002/aelm.202100247Google Scholar25https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB3MXhtFGmtLbL&md5=d75f7744371e82628f408d6d103d4774Operation Principles of ZnO/Al2O3-AlDMP/ZnO Stacked-Channel Ternary Thin-Film TransistorKim, So-Young; Kim, Kiyung; Kim, A. Reum; Lee, Ho-In; Lee, Yongsu; Kim, Seung-Mo; Yu, Sung Ho; Lee, Hae-Won; Hwang, Hyeon Jun; Sung, Myung Mo; Lee, Byoung HunAdvanced Electronic Materials (2021), 7 (6), 2100247CODEN: AEMDBW; ISSN:2199-160X. (Wiley-VCH Verlag GmbH & Co. KGaA)For many decades, novel devices demonstrating step-wise current-voltage characteristic at room temp. have been pursued to realize multi-valued logic computing that has significant advantages such as extremely low power consumption and high-d. information-processing capability. Recently, a novel ternary logic transistor has been constructed using an ultrathin ZnO/Al2O3-AlDMP/ZnO channel exhibiting a mobility edge-quantized conduction for the intermediate current level. This study investigates the operation principle of the ternary device using ZnO/Al2O3-AlDMP/ZnO stack and concludes that the first ZnO layer controls the level of the intermediate current, while the second ZnO layer controls the threshold voltage of the ternary device. These controllable elec. properties of the intermediate state of the ternary device have been applied to an n-type resistive-load std. ternary inverter, demonstrating the feasibility to achieve a ternary logic circuit consuming extremely low power with an optimal noise margin.
- 26Shim, C.-H.; Heo, S.; Noh, J.; Kim, Y. J.; Kim, S.-Y.; Khan, A. K.; Lee, B. H. Design of Ratioless Ternary Inverter Using Graphene Barristor. In 2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) ; 2016; pp 23– 30, DOI: 10.1109/ISMVL.2016.51 .Google ScholarThere is no corresponding record for this reference.
- 27Gupta, A.; Kundu, S.; Teugels, L.; Bommels, J.; Adelmann, C.; Heylen, N.; Jamieson, G.; Pedreira, O. V.; Ciofi, I.; Chava, B.; Wilson, C. J.; Tokei, Z. High-Aspect-Ratio Ruthenium Lines for Buried Power Rail. In 2018 IEEE International Interconnect Technology Conference (IITC) ; 2018; pp 4– 6, DOI: 10.1109/IITC.2018.8430415 .Google ScholarThere is no corresponding record for this reference.
- 28Gupta, A.; Pedreira, O. V.; Arutchelvan, G.; Zahedmanesh, H.; Devriendt, K.; Mertens, H.; Tao, Z.; Ritzenthaler, R.; Wang, S.; Radisic, D.; Kenis, K.; Teugels, L.; Sebai, F.; Lorant, C.; Jourdan, N.; Chan, B. T.; Subramanian, S.; Schleicher, F.; Hopf, T.; Peter, A. P. Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling. IEEE Trans. Electron Devices 2020, 67 (12), 5349– 5354, DOI: 10.1109/TED.2020.3033510Google Scholar28https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB3MXht1Cmt70%253D&md5=cef09a72deab5bfef684f986e2722d8dBuried power rail integration with FinFETs for ultimate CMOS scalingGupta, Anshul; Pedreira, Olalla Varela; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, Katia; Mertens, Hans; Tao, Zheng; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, Boon Teik; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony Premkumar; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Xiuju; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Litta, Eugenio Dentoni; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, Noemie; Sepulveda, A.; Mertens, Sofie; Kim, Min-Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Christel; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano, Efrain; Mitard, Jerome; Wilson, Christopher J.; Holsteyns, Frank; Boemmels, Juergen; Demuynck, Steven; Tokei, Zsolt; Horiguchi, NaotoIEEE Transactions on Electron Devices (2020), 67 (12), 5349-5354CODEN: IETDAI; ISSN:1557-9646. (Institute of Electrical and Electronics Engineers)Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technol. requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degrdn. due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000°C, 1.5 s, without adversely impacting the stack morphol. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielec. plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high m.p. which does not diffuse into dielecs. also minimizes the risk of contamination. To assess the device degrdn., simulations are carried out showing negligible stress transfer from BPR to the channel. This is exptl. validated when no systematic difference in the dc characteristics of CMOS without BPR vs. those in close proximity to floating W-BPR lines is obsd. Addnl., the resistance of the recessed W-BPR line is measured ~ 120 ω/μm for crit. dimension (CD) ~ 32 nm and height ~ 122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330°C, making Ru a candidate for via metalization to achieve low resistance contact strategy to BPR.
- 29Kim, C.; Lee, Y.; Lee, S. Systematic Modulation of Negative-Differential Transconductance Effects for Gated P+-i-N+ Silicon Ultra-Thin Body Transistor. J. Appl. Phys. 2017, 121 (12), 124504, DOI: 10.1063/1.4979213Google Scholar29https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC2sXlt12msLw%253D&md5=f20497b7e78bb363ce266277d997da70Systematic modulation of negative-differential transconductance effects for gated p+-i-n+ silicon ultra-thin body transistorKim, Changmin; Lee, Youngmin; Lee, SejoonJournal of Applied Physics (Melville, NY, United States) (2017), 121 (12), 124504/1-124504/4CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)The authors demonstrate the precise control of the neg.-differential transconductance (NDT) effects on a gated p+-i-n+ Si ultra-thin body transistor. The device clearly displays the N-shape transfer characteristic (i.e., NDT effect) at room temp., and the NDT behavior is fully based on the gate-modulation of the electrostatic junction characteristics. The position and the current level of the peak in the NDT region are systematically controllable when modulating the potential profile at the channel-source junction. Namely, the NDT effect can be systematically modulated through modifying the band-to-band tunneling condition by controlling both gate- and drain-bias voltages. In-depth analyses on the transport characteristics and transport mechanisms are discussed. (c) 2017 American Institute of Physics.
- 30Naquin, C.; Lee, M.; Edwards, H.; Mathur, G.; Chatterjee, T.; Maggio, K. Gate Length and Temperature Dependence of Negative Differential Transconductance in Silicon Quantum Well Metal-Oxide-Semiconductor Field-Effect Transistors. J. Appl. Phys. 2015, 118 (12), 124505, DOI: 10.1063/1.4931662Google Scholar30https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC2MXhsFGksLbF&md5=1760dc610032668aa5d61c9e489c6da6Gate length and temperature dependence of negative differential transconductance in silicon quantum well metal-oxide-semiconductor field-effect transistorsNaquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, KenJournal of Applied Physics (Melville, NY, United States) (2015), 118 (12), 124505/1-124505/6CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)Introducing quantum transport into silicon transistors in a manner compatible with industrial fabrication has the potential to transform the performance horizons of large scale integrated silicon devices and circuits. Explicit quantum transport as evidenced by neg. differential transconductances (NDTCs) was obsd. in a set of quantum well (QW) transistors fabricated using industrial silicon complementary metal-oxide-semiconductor processing. Detailed gate length and temp. dependence characteristics of the NDTCs in these devices were measured. The QW potential was formed via lateral ion implantation doping on a com. 45 nm technol. node process line, and measurements of the transfer characteristics show NDTCs up to room temp. Gate length dependence of NDTCs shows a correlation of the interface channel length with the no. of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temp. dependence is consistent with partial freeze-out of carrier concn. against a degenerately doped background. (c) 2015 American Institute of Physics.
- 31Kim, K. R.; Kim, H. H.; Song, K.-W.; Huh, J. I.; Lee, J. D.; Park, B.-G. Field-Induced Interband Tunneling Effect Transistor (FITET) with Negative-Differential Transconductance and Negative-Differential Conductance. IEEE Transactions on Nanotechnology 2005, 4 (3), 317– 321, DOI: 10.1109/TNANO.2005.847008Google ScholarThere is no corresponding record for this reference.
- 32Zhang, P.; Le, S. T.; Hou, X.; Zaslavsky, A.; Perea, D. E.; Dayeh, S. A.; Picraux, S. T. Strong Room-Temperature Negative Transconductance in an Axial Si/Ge Hetero-Nanowire Tunneling Field-Effect Transistor. Appl. Phys. Lett. 2014, 105 (6), 062106, DOI: 10.1063/1.4892950Google Scholar32https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC2cXhtlGmtr3K&md5=11beab07176541d15cc2ce832c2a2220Strong room-temperature negative transconductance in an axial Si/Ge hetero-nanowire tunneling field-effect transistorZhang, Peng; Le, Son T.; Hou, Xiaoxiao; Zaslavsky, A.; Perea, Daniel E.; Dayeh, Shadi A.; Picraux, S. T.Applied Physics Letters (2014), 105 (6), 062106/1-062106/4CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)The authors report on room-temp. neg. transconductance (NTC) in axial Si/Ge hetero-nanowire tunneling field-effect transistors. The NTC produces a current peak-to-valley ratio >45, a high value for a Si-based device. The authors characterize the NTC over a range of gate VG and drain VD voltages, finding that NTC persists down to VD = -50 mV. The phys. mechanism responsible for the NTC is the VG-induced depletion in the p-Ge section that eventually reduces the max. elec. field that triggers the tunneling ID, as confirmed via three-dimensional (3D) technol. computer-aided design simulations. (c) 2014 American Institute of Physics.
- 33Dey, A. W.; Svensson, J.; Ek, M.; Lind, E.; Thelander, C.; Wernersson, L.-E. Combining Axial and Radial Nanowire Heterostructures: Radial Esaki Diodes and Tunnel Field-Effect Transistors. Nano Lett. 2013, 13 (12), 5919– 5924, DOI: 10.1021/nl4029494Google Scholar33https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC3sXhslOmsLrK&md5=ff5536add353f0e68c715b4b0dba52a3Combining Axial and Radial Nanowire Heterostructures: Radial Esaki Diodes and Tunnel Field-Effect TransistorsDey, Anil W.; Svensson, Johannes; Ek, Martin; Lind, Erik; Thelander, Claes; Wernersson, Lars-ErikNano Letters (2013), 13 (12), 5919-5924CODEN: NALEFD; ISSN:1530-6984. (American Chemical Society)The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit. The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Also, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties. In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a const. drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects; however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require addnl. chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addn. to design advantages of a radial transistor architecture, the authors in this work illustrate the benefit in terms of drive current per unit chip area and compare the exptl. data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the elec. data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. The data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm2, than the max. peak current of axial GaSb/InAs-(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm2, while their axial counterparts at most carry Jpeak = 77 kA/cm2, normalized to the largest cross-sectional area of the nanowire.
- 34Ganjipour, B.; Dey, A. W.; Borg, B. M.; Ek, M.; Pistol, M.-E.; Dick, K. A.; Wernersson, L.-E.; Thelander, C. High Current Density Esaki Tunnel Diodes Based on GaSb-InAsSb Heterostructure Nanowires. Nano Lett. 2011, 11 (10), 4222– 4226, DOI: 10.1021/nl202180bGoogle Scholar34https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC3MXhtFGgtrnI&md5=9b813f5c28272b6fd50091942ce31682High Current Density Esaki Tunnel Diodes Based on GaSb-InAsSb Heterostructure NanowiresGanjipour, Bahram; Dey, Anil W.; Borg, B. Mattias; Ek, Martin; Pistol, Mats-Erik; Dick, Kimberly A.; Wernersson, Lars-Erik; Thelander, ClaesNano Letters (2011), 11 (10), 4222-4226CODEN: NALEFD; ISSN:1530-6984. (American Chemical Society)The authors present elec. characterization of broken gap GaSb-InAsSb nanowire heterojunctions. Esaki diode characteristics with max. reverse current of 1750 kA/cm2 at 0.50 V, max. peak current of 67 kA/cm2 at 0.11 V, and peak-to-valley ratio (PVR) of 2.1 were obtained at room temp. The reverse c.d. is comparable to that of state-of-the-art tunnel diodes based on heavily doped p-n junctions. However, the GaSb-InAsSb diodes studied in this work do not rely on heavy doping, which permits studies of transport mechanisms in simple transistor structures processed with high-κ gate dielecs. and top-gates. Such processing results in devices with improved PVR (3.5) and stability of the elec. properties.
- 35Carnevale, S. D.; Marginean, C.; Phillips, P. J.; Kent, T. F.; Sarwar, A. T. M. G.; Mills, M. J.; Myers, R. C. Coaxial Nanowire Resonant Tunneling Diodes from Non-Polar AlN/GaN on Silicon. Appl. Phys. Lett. 2012, 100 (14), 142115, DOI: 10.1063/1.3701586Google Scholar35https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC38Xlt1elsbk%253D&md5=2a81369f54f45db7bf1f72e8983517d3Coaxial nanowire resonant tunneling diodes from non-polar AlN/GaN on siliconCarnevale, S. D.; Marginean, C.; Phillips, P. J.; Kent, T. F.; Sarwar, A. T. M. G.; Mills, M. J.; Myers, R. C.Applied Physics Letters (2012), 100 (14), 142115/1-142115/4CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)Resonant tunneling diodes are formed using AlN/GaN core-shell nanowire heterostructures grown by plasma assisted MBE on n-Si(111) substrates. By a coaxial geometry, these devices take advantage of non-polar (m-plane) nanowire sidewalls. Device modeling predicts non-polar orientation should enhance resonant tunneling compared to a polar structure, and that AlN double barriers will lead to higher peak-to-valley current ratios compared to AlGaN barriers. Elec. measurements of ensembles of nanowires show neg. differential resistance appearing only at cryogenic temp. Individual nanowire measurements show neg. differential resistance at room temp. with peak c.d. of 5 × 105 A/cm2. (c) 2012 American Institute of Physics.
- 36Nourbakhsh, A.; Zubair, A.; Dresselhaus, M. S.; Palacios, T. Transport Properties of a MoS2/WSe2 Heterojunction Transistor and Its Potential for Application. Nano Lett. 2016, 16 (2), 1359– 1366, DOI: 10.1021/acs.nanolett.5b04791Google Scholar36https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC28XpsFaquw%253D%253D&md5=f7e8e6fb37444d520c25f84947ed6e45Transport Properties of a MoS2/WSe2 Heterojunction Transistor and Its Potential for ApplicationNourbakhsh, Amirhasan; Zubair, Ahmad; Dresselhaus, Mildred S.; Palacios, TomasNano Letters (2016), 16 (2), 1359-1366CODEN: NALEFD; ISSN:1530-6984. (American Chemical Society)This paper studies band-to-band tunneling in the transverse and lateral directions of van der Waals MoS2/WSe2 heterojunctions. We observe room-temp. neg. differential resistance (NDR) in a heterojunction diode comprised of few-layer WSe2 stacked on multilayer MoS2. The presence of NDR is attributed to the lateral band-to-band tunneling at the edge of the MoS2/WSe2 heterojunction. The backward tunneling diode shows an av. conductance slope of 75 mV/dec with a high curvature coeff. of 62 V-1. Assocd. with the tunnel-diode characteristics, a pos.-to-neg. transconductance in the MoS2/WSe2 heterojunction transistors is obsd. The transition is induced by strong interlayer coupling between the films, which results in charge d. and energy-band modulation. The sign change in transconductance is particularly useful for multivalued logic (MVL) circuits, and we therefore propose and demonstrate for the first time an MVL-inverter that shows three levels of logic using one pair of p-type transistors.
- 37Huang, M.; Li, S.; Zhang, Z.; Xiong, X.; Li, X.; Wu, Y. Multifunctional High-Performance van Der Waals Heterostructures. Nat. Nanotechnol. 2017, 12 (12), 1148– 1154, DOI: 10.1038/nnano.2017.208Google Scholar37https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC2sXhs1aisrrJ&md5=893ea0a9674bb9dab8d016a4a3c87658Multifunctional high-performance van der Waals heterostructuresHuang, Mingqiang; Li, Shengman; Zhang, Zhenfeng; Xiong, Xiong; Li, Xuefei; Wu, YanqingNature Nanotechnology (2017), 12 (12), 1148-1154CODEN: NNAABX; ISSN:1748-3387. (Nature Research)A range of novel two-dimensional materials have been actively explored for More Moore and More-than-Moore device applications because of their ability to form van der Waals heterostructures with unique electronic properties. However, most of the reported electronic devices exhibit insufficient control of multifunctional operations. Here, we leverage the band-structure alignment properties of narrow-bandgap black phosphorus and large-bandgap molybdenum disulfide to realize vertical heterostructures with an ultrahigh rectifying ratio approaching 106 and on-off ratio up to 107. Furthermore, we design and fabricate tunable multivalue inverters, in which the output logic state and window of the mid-logic can be controlled by specific pairs of channel length and, most importantly, by the elec. field, which shifts the band-structure alignment across the heterojunction. Finally, high gains over 150 are achieved in the inverters with optimized device geometries, showing great potential for future logic applications.
- 38Lv, W.; Fu, X.; Luo, X.; Lv, W.; Cai, J.; Zhang, B.; Wei, Z.; Liu, Z.; Zeng, Z. Multistate Logic Inverter Based on Black Phosphorus/SnSeS Heterostructure. Adv. Electron. Mater. 2019, 5 (1), 1800416, DOI: 10.1002/aelm.201800416Google ScholarThere is no corresponding record for this reference.
- 39Xiong, X.; Kang, J.; Hu, Q.; Gu, C.; Gao, T.; Li, X.; Wu, Y. Reconfigurable Logic-in-Memory and Multilingual Artificial Synapses Based on 2D Heterostructures. Adv. Funct. Mater. 2020, 30 (11), 1909645, DOI: 10.1002/adfm.201909645Google Scholar39https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB3cXitFeks78%253D&md5=743da77f300c304024d1c427a5c331a0Reconfigurable logic-in-memory and multilingual artificial synapses based on 2D heterostructuresXiong, Xiong; Kang, Jiyang; Hu, Qianlan; Gu, Chengru; Gao, Tingting; Li, Xuefei; Wu, YanqingAdvanced Functional Materials (2020), 30 (11), 1909645CODEN: AFMDC6; ISSN:1616-301X. (Wiley-VCH Verlag GmbH & Co. KGaA)Nonvolatile logic devices have attracted intensive research attentions recently for energy efficiency computing, where data computing and storage can be realized in the same device structure. Various approaches have been adopted to build such devices; however, the functionality and versatility are still very limited. Here, 2-dimensional van der Waals heterostructures based on direct band gap materials black phosphorus and rhenium disulfide for the nonvolatile ternary logic operations is demonstrated for the first time with the ultrathin oxide layer from the black phosphorus serving as the charge trapping as well as band-to-band tunneling layer. Furthermore, an artificial electronic synapse based on this heterostructure is demonstrated to mimic trilingual synaptic response by changing the input base voltage. Besides, artificial neural network simulation based on the electronic synaptic arrays using the handwritten digits data sets demonstrates a high recognition accuracy of 91.3%. This work provides a path toward realizing multifunctional nonvolatile logic-in-memory applications based on novel 2D heterostructures.
- 40Dong, J.; Liu, F.; Wang, F.; Wang, J.; Li, M.; Wen, Y.; Wang, L.; Wang, G.; He, J.; Jiang, C. Configuration-Dependent Anti-Ambipolar van Der Waals p–n Heterostructures Based on Pentacene Single Crystal and MoS2. Nanoscale 2017, 9 (22), 7519– 7525, DOI: 10.1039/C7NR01822CGoogle Scholar40https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC2sXns1GrsLs%253D&md5=4bbcdeb075cb3a9276ba60b13b83fffdConfiguration-dependent anti-ambipolar van der Waals p-n heterostructures based on pentacene single crystal and MoS2Dong, Ji; Liu, Fengjing; Wang, Feng; Wang, Jiawei; Li, Molin; Wen, Yao; Wang, Liang; Wang, Gongtang; He, Jun; Jiang, ChaoNanoscale (2017), 9 (22), 7519-7525CODEN: NANOHL; ISSN:2040-3372. (Royal Society of Chemistry)Recently, van der Waals heterostructures (vdWHs) have trigged intensive interest due to their novel electronic and optoelectronic properties. The vdWHs could be achieved by stacking two dimensional layered materials (2DLMs) on top of another and vertically kept by van der Waals forces. Furthermore, org. semiconductors are also known to interact via van der Waals forces, which offer an alternative for the fabrication of org.-inorg. p-n vdWHs. However, the performances of org.-inorg. p-n vdWHs produced so far are rather poor, owing to the unmatched elec. property between the 2DLMs and org. polycryst. films. To make improvements in such novel heterostructure architectures, here we adopt high quality org. single crystals instead of polycryst. films to construct a pentacene/MoS2 p-n vdWH. The vdWHs show a much higher c.d. and better anti-ambipolar characteristics with a highest transconductance of 211 nS. Moreover, device configuration-dependent transfer characteristics are demonstrated and a mechanism of a gate bias modulated vertical space charge zone existing at the vertical p-n vdWHs interface is proposed. These findings provide a new route to optimize the org.-inorg. p-n vdWHs and a guideline for studying the intrinsic properties of vdWHs.
- 41Li, S.; Chen, X.; Liu, L.; Zeng, Z.; Chang, S.; Wang, H.; Wu, H.; Long, S.; Liu, C. Micron Channel Length ZnO Thin Film Transistors Using Bilayer Electrodes. J. Colloid Interface Sci. 2022, 622, 769– 779, DOI: 10.1016/j.jcis.2022.04.016Google Scholar41https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB38Xht1antL3M&md5=1e625748e86389d43a8e3f6368a23506Micron channel length ZnO thin film transistors using bilayer electrodesLi, Sizhe; Chen, Xue; Liu, Li; Zeng, Zhiyu; Chang, Sheng; Wang, Hao; Wu, Hao; Long, Shibing; Liu, ChangJournal of Colloid and Interface Science (2022), 622 (), 769-779CODEN: JCISA5; ISSN:0021-9797. (Elsevier B.V.)Micro light-emitting diodes (Micro-LEDs) are currently attracting more and more attention. Thin film transistors (TFTs) with micron channel lengths can be used to drive Micro-LEDs. The key parameters of TFTs, such as mobility, ION/IOFF and threshold voltage, still need to be improved. In this study, we propose and exptl. demonstrate ZnO TFTs using bilayer electrodes to overcome the short channel effects when the channel length is scaled down to 3μm. Ti, Mo and Sn interlayers not only serve as diffusion barriers to prohibit migration of Cu atoms from the top electrodes, but also enhance adhesive energy of the metal electrodes on ZnO channel layers. ZnO TFTs using Cu/Ti bilayer electrodes exhibit the best performance, e.g., a high mobility of 45.3 cm2V-1s-1, a high ION/IOFF ratio of 4.28 x 109, a low subthreshold of 0.24 V/dec and a proper threshold voltage of 1.13 V. The high mobility can be attributed to a significant decrease of the barrier height and a slight narrowing of the space charge layer, and the high ratio of ION/IOFF is concerned with the high electron concn. under an ON-state condition. Thus, ZnO TFTs using Cu/Ti bilayer electrodes can be used in next-generation displays.
- 42Li, H.; Han, D.; Dong, J.; Yi, Z.; Zhou, X.; Zhang, S.; Zhang, X.; Wang, Y. Enhanced Performance of Atomic Layer Deposited Thin-Film Transistors With High-Quality ZnO/Al2O3 Interface. IEEE Trans. Electron Devices 2020, 67 (2), 518– 523, DOI: 10.1109/TED.2019.2957048Google Scholar42https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB3cXhslChsL7N&md5=82078c9e7cdbf11913133ea58488646dEnhanced performance of atomic layer deposited thin-film transistors with high-quality ZnO/Al2O3 interfaceLi, Huijin; Han, Dedong; Dong, Junchen; Yi, Zhuang; Zhou, Xiaobin; Zhang, Shengdong; Zhang, Xing; Wang, YiIEEE Transactions on Electron Devices (2020), 67 (2), 518-523CODEN: IETDAI; ISSN:1557-9646. (Institute of Electrical and Electronics Engineers)We fabricated ZnO channel/Al2O3 gate dielec. thin-film transistors (TFTs) by at. layer deposition (ALD) continuous growth process. The effects of the channel and the dielec. continuous growth on the performance of TFTs were investigated. Compared with noncontinuous growth ZnO/Al2O3 films, continuous growth ZnO/Al2O3 films with no obvious buffer layer and less residual O-H bonds possess superior ZnO/Al2O3 interface quality. The continuous growth TFTs exhibit a field-effect mobility of 19.6 cm2 V-1s-1, a subthreshold swing of 0.13 V dec-1, a high ION/IOFF of 4.1 x 109, a hysteresis window of 0.09 V, and an excellent uniformity of elec. characteristics. Continuous growth TFTs also demonstrate better stability with minor shifts of Vth 0.6 V [pos. bias stress (PBS)] and Vth - 0.3 V [neg. bias stress (NBS)]. The faster falling rates of activation energy for continuous growth TFTs indicate that the total trap d. is reduced through the continuous growth of active layer and dielec. layer. Our results suggest that the ALD-based continuous growth process could enhance the performance of TFTs.
- 43Acharya, R.; Günder, D.; Breuer, T.; Schmitz, G.; Klauk, H.; Witte, G. Stability of Organic Thin-Film Transistors Based on Ultrathin Films of Dinaphtho[2,3-b:2′,3′-f]Thieno[3,2- b]Thiophene (DNTT). Journal of Materials Chemistry C 2021, 9 (1), 270– 280, DOI: 10.1039/D0TC04554CGoogle Scholar43https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB3cXisVSks7zE&md5=253a62526f72be625ae2c3a1cb14f54bStability of organic thin-film transistors based on ultrathin films of dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT)Acharya, Rachana; Guender, Darius; Breuer, Tobias; Schmitz, Guido; Klauk, Hagen; Witte, GregorJournal of Materials Chemistry C: Materials for Optical and Electronic Devices (2021), 9 (1), 270-280CODEN: JMCCCX; ISSN:2050-7534. (Royal Society of Chemistry)Org. thin-film transistors (TFTs) based on ultrathin semiconductor films are potentially useful as highly sensitive phys., chem. or biol. sensors and may also help in the development of a better understanding of the relations between structural and charge-transport characteristics of thin films of org. semiconductors. A particularly promising small-mol. org. semiconductor is dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT). However, it was recently reported that ultrathin DNTT films spontaneously undergo dramatic morphol. changes within minutes after deposition that lead to the disaggregation of the initially closed (or at least connected) single-monolayer films into disconnected multilayer islands. Here, we investigate how this spontaneous structural reconfiguration affects the characteristics of TFTs based on ultrathin DNTT films and explore the extent to which it can be prevented by cryogenic cooling or in situ encapsulation. We fabricated inverted coplanar TFTs with a hybrid aluminum oxide/alkylphosphonic acid self-assembled monolayer gate dielec. and vacuum-deposited DNTT films with nominal thicknesses of 2.5 or 25 nm. Using at. force microscopy (AFM) we monitored the spontaneous changes in the DNTT morphol. in a quasi-continuous manner over a period of 12 h after deposition. The charge-carrier mobility of the ultrathin DNTT TFTs was found to decrease rapidly, while the mobility of the TFTs with the thicker DNTT films is far more stable. We also found that the initial closed-monolayer morphol. of the ultrathin DNTT films is preserved when the substrates are cooled to cryogenic temps. immediately after the DNTT deposition, but that the morphol. changes resume upon returning the substrates to room temp. Furthermore, we fabricated TFTs in which the ultrathin DNTT films were encapsulated in situ with a vacuum-deposited film of polytetrafluoroethylene, C60 or titanyl phthalocyanine immediately following the DNTT deposition and found that the encapsulation decelerates the structural reorganization of the ultrathin DNTT films and the concurrent degrdn. of the carrier mobility.
- 44Ibrahim, G. H.; Zschieschang, U.; Klauk, H.; Reindl, L. High-Frequency Rectifiers Based on Organic Thin-Film Transistors on Flexible Substrates. IEEE Trans. Electron Devices 2020, 67 (6), 2365– 2371, DOI: 10.1109/TED.2020.2989730Google Scholar44https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB3cXhvFantrnK&md5=077a690b8f6ac52ec1ea14bb606d1d4eHigh-frequency rectifiers based on organic thin-film transistors on flexible substratesIbrahim, Ghada H.; Zschieschang, Ute; Klauk, Hagen; Reindl, LeonhardIEEE Transactions on Electron Devices (2020), 67 (6), 2365-2371CODEN: IETDAI; ISSN:1557-9646. (Institute of Electrical and Electronics Engineers)Rectifier circuits featuring low threshold voltages and high cutoff frequencies based on p-channel org. thin-film transistors (TFTs) have been designed, fabricated and characterized. The TFTs and circuits were fabricated by shadow-mask lithog. on flexible plastic substrates using the vacuum-deposited small-mol. org. semiconductor dinaphtho[2,3-b:2',3'-f]thieno[3,2-b] thiophene (DNTT). The TFTs have a gate dielec. with a thickness of 5.3 nm and a channel length of 10μm. The study considers the frequency characteristics of diode-connected transistors (transdiodes) and adopts circuit techniques from silicon CMOS technol., namely single-stage and multistage dynamic-threshold-compensated differential rectifiers. The characterization of the rectifier circuits indicates cutoff frequencies up to 4.75 MHz at a peak-to-peak input voltage of 3 V for transdiodes, up to 32 MHz at a peak-to-peak input voltage of 1.5 V for single-stage differential rectifiers and up to 7.5 MHz at a peak-to-peak input voltage of 1.5 V for two-stage rectifiers. The efficiency is 25% for a load of 10 MΩ and below 1% for a load of 1 MΩ.
- 45Kobashi, K.; Hayakawa, R.; Chikyow, T.; Wakayama, Y. Negative Differential Resistance Transistor with Organic P-n Heterojunction. Adv. Electron. Mater. 2017, 3 (8), 1700106, DOI: 10.1002/aelm.201700106Google ScholarThere is no corresponding record for this reference.
- 46On, S.; Kim, Y.-J.; Lee, H.-K.; Yoo, H. Ambipolar and Anti-Ambipolar Thin-Film Transistors from Edge-on Small-Molecule Heterostructures. Appl. Surf. Sci. 2021, 542, 148616, DOI: 10.1016/j.apsusc.2020.148616Google Scholar46https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB3cXisFyqs7nE&md5=fac3852dd0610f8fd4e66f2f6545e8abAmbipolar and anti-ambipolar thin-film transistors from edge-on small-molecule heterostructuresOn, Sungmin; Kim, Young-Joon; Lee, Han-Koo; Yoo, HocheonApplied Surface Science (2021), 542 (), 148616CODEN: ASUSEE; ISSN:0169-4332. (Elsevier B.V.)Heterostructure electronic devices potentially provide opportunities for novel transistor operations, including ambipolar and anti-ambipolar switching characteristics. However, there are still no previous studies investigating the phys., chem., and morphol. properties of small-mol. semiconductor films deposited as heterojunctions. Here, we systemically investigate chem. and morphol. structure in a heterostructure of small-mol. org. semiconductors using XPS, near-edge X-ray absorption of fine structure (NEXAFS), and UPS (UPS). The anal. reveals that dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) and N,N'-ditridecylperylenediimide (PTCDI-C13) maintain their chem. compns., energy structure, and edge-on mol. orientations (tilt angle = 66°). Furthermore, ambipolar and anti-ambipolar transistors are demonstrated using the edge-on DNTT/PTCDI-C13 heterostructure. These transistors enable CMOS-like inverter and ternary inverter operations as resp. example applications of ambipolar and anti-ambipolar transistors.
- 47Nakata, M.; Tsuji, H.; Sato, H.; Nakajima, Y.; Fujisaki, Y.; Takei, T.; Yamamoto, T.; Fujikake, H. Influence of Oxide Semiconductor Thickness on TFT Characteristics. 2012 19th International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD) ; 2012.Google ScholarThere is no corresponding record for this reference.
- 48Chang, J.-F.; Shie, H.-S.; Yang, Y.-W.; Wang, C.-H. Study on Correlation between Structural and Electronic Properties of Fluorinated Oligothiophenes Transistors by Controlling Film Thickness. Crystals 2019, 9 (3), 144, DOI: 10.3390/cryst9030144Google Scholar48https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC1MXovV2nsbc%253D&md5=3c885f2028c21db625d975f022d61a35Study on correlation between structural and electronic properties of fluorinated oligothiophenes transistors by controlling film thicknessChang, Jui-Fen; Shie, Hua-Shiuan; Yang, Yaw-Wen; Wang, Chia-HsinCrystals (2019), 9 (3), 144/1-144/14CODEN: CRYSBC; ISSN:2073-4352. (MDPI AG)α,ω-Diperfluorohexylquaterthiophene (DFH-4T) has been an attractive n-type material employed in the development of high-mobility org. field-effect transistors. This paper presents a systematic study of the relationship between DFH-4T transistor performance and film structure properties as controlled by deposited thickness. When the DFH-4T thickness increases from 8 nm to 80 nm, the room-temp. field-effect mobility increases monotonically from 0.01 to 1 cm2·V-1·s-1, while the threshold voltage shows a different trend of first decrease then increase. The morphol. of thin films revealed by at. force microscopy shows a dramatic change from multilayered terrace to stacked rod like structures as the film thickness is increased. Yet the crystallite structure and the orientation of mol. constituent, as detd. by X-ray diffraction and near-edge X-ray absorption fine structure resp., do not differ much with respect to film thickness increase. Further analyses of low-temp. transport measurements with mobility-edge model demonstrate that the electronic states of DFH-4T transistors are mainly detd. by the film continuity and crystallinity of the bottom multilayered terrace. Moreover, the capacitance-voltage measurements of DFH-4T metal-insulator-semiconductor diodes demonstrate a morphol. dependence of charge injection from top contacts, which well explains the variation of threshold voltage with thickness. The overall study provides a deeper understanding of microstructural and mol. growth of DFH-4T film and clarify the structural effects on charge transport and injection for implementation of high-mobility top-contact transistors.
- 49Lovie, P. Coefficient of Variation. Encyclopedia of Statistics in Behavioral Science; John Wiley & Sons, Ltd.: Chichester, 2005; Vol. 1, pp 317– 318, DOI: 10.1002/0470013192.bsa107 .Google ScholarThere is no corresponding record for this reference.
- 50Stanford University CNTFET Model, https://nano.stanford.edu/downloads/stanford-cnfet-model (accessed Feb 14, 2022).Google ScholarThere is no corresponding record for this reference.
- 51Predictive Technology Model (PTM), http://ptm.asu.edu (accessed Feb 14, 2022).Google ScholarThere is no corresponding record for this reference.
- 52Etiemble, D. Comparing Ternary and Binary Adders and Multipliers. 2019, arXiv:1908.07299, https://arxiv.org/abs/1908.07299 (accessed Feb 8, 2022).Google ScholarThere is no corresponding record for this reference.
- 53Lee, S.; Striakhilev, D.; Jeon, S.; Nathan, A. Unified Analytic Model for Current–Voltage Behavior in Amorphous Oxide Semiconductor TFTs. IEEE Electron Device Lett. 2014, 35 (1), 84– 86, DOI: 10.1109/LED.2013.2290532Google Scholar53https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC2cXjtlWlsLg%253D&md5=1e4149e52f481aff0f05012c36e8bbf6Unified analytic model for current-voltage behavior in amorphous oxide semiconductor TFTsLee, Sungsik; Striakhilev, Denis; Jeon, Sanghun; Nathan, ArokiaIEEE Electron Device Letters (2014), 35 (1), 84-86CODEN: EDLEDZ; ISSN:0741-3106. (Institute of Electrical and Electronics Engineers)We present a simple and semi-phys. anal. description of the current-voltage characteristics of amorphous oxide semiconductor thin-film transistors in the above-threshold and sub-threshold regions. Both regions are described by single unified expression that employs the same set of model parameter values directly extd. from measured terminal characteristics. The model accurately reproduces measured characteristics of amorphous semiconductor thin film transistors in general, yielding a scatter of <4%.
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This article references 53 other publications.
- 1Moore, G. E. Cramming More Components onto Integrated Circuits. Proc. IEEE 1998, 86 (1), 4, DOI: 10.1109/JPROC.1998.658762There is no corresponding record for this reference.
- 2Hiramoto, T. Five Nanometre CMOS Technology. Nat. Electron 2019, 2 (12), 557– 558, DOI: 10.1038/s41928-019-0343-xThere is no corresponding record for this reference.
- 3Khan, H. N.; Hounshell, D. A.; Fuchs, E. R. H. Science and Research Policy at the End of Moore’s Law. Nat. Electron 2018, 1 (1), 14– 21, DOI: 10.1038/s41928-017-0005-9There is no corresponding record for this reference.
- 4Salahuddin, S.; Ni, K.; Datta, S. The Era of Hyper-Scaling in Electronics. Nat. Electron 2018, 1 (8), 442– 450, DOI: 10.1038/s41928-018-0117-xThere is no corresponding record for this reference.
- 5Akinwande, D.; Huyghebaert, C.; Wang, C.-H.; Serna, M. I.; Goossens, S.; Li, L.-J.; Wong, H.-S. P.; Koppens, F. H. L. Graphene and Two-Dimensional Materials for Silicon Technology. Nature 2019, 573 (7775), 507– 518, DOI: 10.1038/s41586-019-1573-95https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC1MXhvVCmu73F&md5=458f9a3e7f71f5718f0bd150c54bdb2dGraphene and two-dimensional materials for silicon technologyAkinwande, Deji; Huyghebaert, Cedric; Wang, Ching-Hua; Serna, Martha I.; Goossens, Stijn; Li, Lain-Jong; Wong, H.-S. Philip; Koppens, Frank H. L.Nature (London, United Kingdom) (2019), 573 (7775), 507-518CODEN: NATUAS; ISSN:0028-0836. (Nature Research)The development of silicon semiconductor technol. has produced breakthroughs in electronics-from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones-by downscaling the phys. size of devices and wires to the nanometer regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device performance at the at. limit, and a synergistic combination of 2D materials with silicon chips promises a heterogeneous platform to deliver massively enhanced potential based on silicon technol. Integration is achieved via three-dimensional monolithic construction of multifunctional high-rise 2D silicon chips, enabling enhanced performance by exploiting the vertical direction and the functional diversification of the silicon platform for applications in opto-electronics and sensing. Here we review the opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems, and also consider the prospects for computational and non-computational applications.
- 6Son, Y.; Frost, B.; Zhao, Y.; Peterson, R. L. Monolithic Integration of High-Voltage Thin-Film Electronics on Low-Voltage Integrated Circuits Using a Solution Process. Nat. Electron 2019, 2 (11), 540– 548, DOI: 10.1038/s41928-019-0316-06https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC1MXitFOltb7N&md5=b0c680377630015e231dc722a49cf767Monolithic integration of high-voltage thin-film electronics on low-voltage integrated circuits using a solution processSon, Youngbae; Frost, Brad; Zhao, Yunkai; Peterson, Rebecca L.Nature Electronics (2019), 2 (11), 540-548CODEN: NEALB3; ISSN:2520-1131. (Nature Research)The performance of silicon complementary metal-oxide-semiconductor integrated circuits can be enhanced through the monolithic three-dimensional integration of addnl. device layers. For example, silicon integrated circuits operate at low voltages (around 1 V) and high-voltage handling capabilities could be provided by monolithically integrating thin-film transistors. Here we show that high-voltage amorphous oxide semiconductor thin-film transistors can be integrated on top of a silicon integrated circuit contg. 100-nm-node fin field-effect transistors using an in-air soln. process. To solve the problem of voltage mismatch between these two device layers, we use a top Schottky, bottom ohmic contact structure to reduce the amorphous oxide semiconductor circuit switching voltage. These contacts are used to form Schottky-gated thin-film transistors and vertical thin-film diodes with excellent switching performance. As a result, we can create high-voltage amorphous oxide semiconductor circuits with switching voltages less than 1.2 V that can be directly integrated with silicon integrated circuits.
- 7Choi, J.; Han, J. S.; Hong, K.; Kim, S. Y.; Jang, H. W. Organic–Inorganic Hybrid Halide Perovskites for Memories, Transistors, and Artificial Synapses. Adv. Mater. 2018, 30 (42), 1704002, DOI: 10.1002/adma.201704002There is no corresponding record for this reference.
- 8Andrae, A. S. G.; Edler, T. On Global Electricity Usage of Communication Technology: Trends to 2030. Challenges 2015, 6 (1), 117– 157, DOI: 10.3390/challe6010117There is no corresponding record for this reference.
- 9Shibata, T.; Ohmi, T. A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations. IEEE Trans. Electron Devices 1992, 39 (6), 1444– 1455, DOI: 10.1109/16.137325There is no corresponding record for this reference.
- 10Rine, D. C. Computer Science and Multiple-Valued Logic: Theory and Applications; Elsevier: Amsterdam, 1977.There is no corresponding record for this reference.
- 11Gaudet, V. A Survey and Tutorial on Contemporary Aspects of Multiple-Valued Logic and Its Application to Microelectronic Circuits. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2016, 6 (1), 5– 12, DOI: 10.1109/JETCAS.2016.2528041There is no corresponding record for this reference.
- 12Smith The Prospects for Multivalued Logic: A Technology and Applications View. IEEE Transactions on Computers 1981, C–30 (9), 619– 634, DOI: 10.1109/TC.1981.1675860There is no corresponding record for this reference.
- 13Chen, W.-H.; Dou, C.; Li, K.-X.; Lin, W.-Y.; Li, P.-Y.; Huang, J.-H.; Wang, J.-H.; Wei, W.-C.; Xue, C.-X.; Chiu, Y.-C.; King, Y.-C.; Lin, C.-J.; Liu, R.-S.; Hsieh, C.-C.; Tang, K.-T.; Yang, J. J.; Ho, M.-S.; Chang, M.-F. CMOS-Integrated Memristive Non-Volatile Computing-in-Memory for AI Edge Processors. Nat. Electron 2019, 2 (9), 420– 428, DOI: 10.1038/s41928-019-0288-013https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC1MXhs1Gisr3K&md5=7b4b668979e49a7839eb7632750a244fCMOS-integrated memristive non-volatile computing-in-memory for AI edge processorsChen, Wei-Hao; Dou, Chunmeng; Li, Kai-Xiang; Lin, Wei-Yu; Li, Pin-Yi; Huang, Jian-Hao; Wang, Jing-Hong; Wei, Wei-Chen; Xue, Cheng-Xin; Chiu, Yen-Cheng; King, Ya-Chin; Lin, Chorng-Jung; Liu, Ren-Shuo; Hsieh, Chih-Cheng; Tang, Kea-Tiong; Yang, J. Joshua; Ho, Mon-Shu; Chang, Meng-FanNature Electronics (2019), 2 (9), 420-428CODEN: NEALB3; ISSN:2520-1131. (Nature Research)Non-volatile computing-in-memory (nvCIM) could improve the energy efficiency of edge devices for artificial intelligence applications. The basic functionality of nvCIM has recently been demonstrated using small-capacity memristor crossbar arrays combined with peripheral readout circuits made from discrete components. However, the advantages of the approach in terms of energy efficiency and operating speeds, as well as its robustness against device variability and sneak currents, have yet to be demonstrated exptl. Here, we report a fully integrated memristive nvCIM structure that offers high energy efficiency and low latency for Boolean logic and multiply-and-accumulation (MAC) operations. We fabricate a 1 Mb resistive random-access memory (ReRAM) nvCIM macro that integrates a one-transistor-one-resistor ReRAM array with control and readout circuits on the same chip using an established 65 nm foundry complementary metal-oxide-semiconductor (CMOS) process. The approach offers an access time of 4.9 ns for three-input Boolean logic operations, a MAC computing time of 14.8 ns and an energy efficiency of 16.95 tera operations per s per W. Applied to a deep neural network using a split binary-input ternary-weighted model, the system can achieve an inference accuracy of 98.8% on the MNIST dataset.
- 14Yang, R.; Li, H.; Smithe, K. K. H.; Kim, T. R.; Okabe, K.; Pop, E.; Fan, J. A.; Wong, H.-S. P. Ternary Content-Addressable Memory with MoS2 Transistors for Massively Parallel Data Search. Nat. Electron 2019, 2 (3), 108– 114, DOI: 10.1038/s41928-019-0220-7There is no corresponding record for this reference.
- 15Kim, K.; Kim, S.; Lee, Y.; Kim, D.; Kim, S.-Y.; Kang, S.; Lee, B. H. Extreme Low Power Technology Using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction. In 2020 IEEE 50th International Symposium on Multiple-Valued Logic (ISMVL) ; 2020; pp 155– 158, DOI: 10.1109/ISMVL49045.2020.00-13 .There is no corresponding record for this reference.
- 16Kim, Y. J.; Kim, S.-Y.; Noh, J.; Shim, C. H.; Jung, U.; Lee, S. K.; Chang, K. E.; Cho, C.; Lee, B. H. Demonstration of Complementary Ternary Graphene Field-Effect Transistors. Sci. Rep 2016, 6 (1), 39353, DOI: 10.1038/srep3935316https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC28XitFGjtLnM&md5=9c2ec2bd568c4d429fe1274d6dacca9cDemonstration of Complementary Ternary Graphene Field-Effect TransistorsKim, Yun Ji; Kim, So-Young; Noh, Jinwoo; Shim, Chang Hoo; Jung, Ukjin; Lee, Sang Kyung; Chang, Kyoung Eun; Cho, Chunhum; Lee, Byoung HunScientific Reports (2016), 6 (), 39353CODEN: SRCEC3; ISSN:2045-2322. (Nature Publishing Group)Strong demand for power redn. in state-of-the-art semiconductor devices calls for novel devices and architectures. Since ternary logic architecture can perform the same function as binary logic architecture with a much lower device d. and higher information d., a switch device suitable for the ternary logic has been pursued for several decades. However, a single device that satisfies all the requirements for ternary logic architecture has not been demonstrated. We demonstrated a ternary graphene field-effect transistor (TGFET), showing three discrete current states in one device. The ternary function was achieved by introducing a metal strip to the middle of graphene channel, which created an N-P-N or P-N-P doping pattern depending on the work function of the metal. In addn., a std. ternary inverter working at room temp. has been achieved by modulating the work function of the metal in a graphene channel. The feasibility of a ternary inverter indicates that a general ternary logic architecture can be realized using complementary TGFETs. This breakthrough will provide a key stepping-stone for an extreme-low-power computing technol.
- 17Raychowdhury, A.; Roy, K. Carbon-Nanotube-Based Voltage-Mode Multiple-Valued Logic Design. IEEE Transactions on Nanotechnology 2005, 4 (2), 168– 179, DOI: 10.1109/TNANO.2004.842068There is no corresponding record for this reference.
- 18Lin, S.; Kim, Y.-B.; Lombardi, F. CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits. IEEE Transactions on Nanotechnology 2011, 10 (2), 217– 225, DOI: 10.1109/TNANO.2009.2036845There is no corresponding record for this reference.
- 19Kim, S.; Lim, T.; Kang, S. An Optimal Gate Design for the Synthesis of Ternary Logic Circuits. In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) ; 2018; pp 476– 481, DOI: 10.1109/ASPDAC.2018.8297369 .There is no corresponding record for this reference.
- 20Karmakar, S.; Chandy, J. A.; Jain, F. C. Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2013, 21 (5), 793– 806, DOI: 10.1109/TVLSI.2012.2198248There is no corresponding record for this reference.
- 21Heo, S.; Kim, S.; Kim, K.; Lee, H.; Kim, S.-Y.; Kim, Y. J.; Kim, S. M.; Lee, H.-I.; Lee, S.; Kim, K. R.; Kang, S.; Lee, B. H. Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors. IEEE Electron Device Lett. 2018, 39 (12), 1948– 1951, DOI: 10.1109/LED.2018.287405521https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC1MXhtFWhtr3N&md5=95e1cddf5208bc5fb34d23858c1023eaTernary full adder using multi-threshold voltage graphene barristorsHeo, Sunwoo; Kim, Sunmean; Kim, Kiyung; Lee, Hyeji; Kim, So-Young; Kim, Yun Ji; Kim, Seung Mo; Lee, Ho-In; Lee, Segi; Kim, Kyung Rok; Kang, Seokhyeong; Lee, Byoung HunIEEE Electron Device Letters (2018), 39 (12), 1948-1951CODEN: EDLEDZ; ISSN:1558-0563. (Institute of Electrical and Electronics Engineers)Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ∼10-16 J, which is comparable to the binary equiv. circuit. The ternary full adder was modeled using device parameters extd. from the exptl. demonstrated multi-Vth ternary graphene barristors.
- 22Kim, S.-Y.; Heo, S.; Kim, K.; Son, M.; Kim, S.-M.; Lee, H.-I.; Lee, Y.; Hwang, H. J.; Ham, M.-H.; Lee, B. H. Demonstration of Ternary Devices and Circuits Using Dual Channel Graphene Barristors. In 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL); IEEE: Fredericton, NB, Canada, 2019; pp 25– 30, DOI: 10.1109/ISMVL.2019.00013 .There is no corresponding record for this reference.
- 23Lee, Y.; Kim, S.-M.; KIM, K.; Kim, S.-Y.; Lee, H.-I.; Kwon, H.; Lee, H.-W.; Kim, C.; Some, S.; Hwang, H. J.; Lee, B. H. Dual-Channel P-Type Ternary DNTT–Graphene Barristor. Submitted to Sci. Rep. 2022.There is no corresponding record for this reference.
- 24Lee, L.; Hwang, J.; Jung, J. W.; Kim, J.; Lee, H.-I.; Heo, S.; Yoon, M.; Choi, S.; Van Long, N.; Park, J.; Jeong, J. W.; Kim, J.; Kim, K. R.; Kim, D. H.; Im, S.; Lee, B. H.; Cho, K.; Sung, M. M. ZnO Composite Nanolayer with Mobility Edge Quantization for Multi-Value Logic Transistors. Nat. Commun. 2019, 10 (1), 1998, DOI: 10.1038/s41467-019-09998-x24https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A280%3ADC%252BB3M7gvFerug%253D%253D&md5=67e9f17c4e388b98aa5e5ed2529dcb49ZnO composite nanolayer with mobility edge quantization for multi-value logic transistorsLee Lynn; Jung Jin Won; Kim Jongchan; Van Long Nguyen; Park Jinseon; Sung Myung Mo; Hwang Jeongwoon; Kim Jiyoung; Cho Kyeongjae; Hwang Jeongwoon; Lee Ho-In; Heo Sunwoo; Lee Byoung Hun; Yoon Minho; Im Seongil; Choi Sungju; Kim Dae Hwan; Jeong Jae Won; Kim Kyung RokNature communications (2019), 10 (1), 1998 ISSN:.A quantum confined transport based on a zinc oxide composite nanolayer that has conducting states with mobility edge quantization is proposed and was applied to develop multi-value logic transistors with stable intermediate states. A composite nanolayer with zinc oxide quantum dots embedded in amorphous zinc oxide domains generated quantized conducting states at the mobility edge, which we refer to as "mobility edge quantization". The unique quantized conducting state effectively restricted the occupied number of carriers due to its low density of states, which enable current saturation. Multi-value logic transistors were realized by applying a hybrid superlattice consisting of zinc oxide composite nanolayers and organic barriers as channels in the transistor. The superlattice channels produced multiple states due to current saturation of the quantized conducting state in the composite nanolayers. Our multi-value transistors exhibited excellent performance characteristics, stable and reliable operation with no current fluctuation, and adjustable multi-level states.
- 25Kim, S.; Kim, K.; Kim, A. R.; Lee, H.; Lee, Y.; Kim, S.; Yu, S. H.; Lee, H.; Hwang, H. J.; Sung, M. M.; Lee, B. H. Operation Principles of ZnO/Al2O3-AlDMP/ZnO Stacked-Channel Ternary Thin-Film Transistor. Adv. Electron. Mater. 2021, 7 (6), 2100247, DOI: 10.1002/aelm.20210024725https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB3MXhtFGmtLbL&md5=d75f7744371e82628f408d6d103d4774Operation Principles of ZnO/Al2O3-AlDMP/ZnO Stacked-Channel Ternary Thin-Film TransistorKim, So-Young; Kim, Kiyung; Kim, A. Reum; Lee, Ho-In; Lee, Yongsu; Kim, Seung-Mo; Yu, Sung Ho; Lee, Hae-Won; Hwang, Hyeon Jun; Sung, Myung Mo; Lee, Byoung HunAdvanced Electronic Materials (2021), 7 (6), 2100247CODEN: AEMDBW; ISSN:2199-160X. (Wiley-VCH Verlag GmbH & Co. KGaA)For many decades, novel devices demonstrating step-wise current-voltage characteristic at room temp. have been pursued to realize multi-valued logic computing that has significant advantages such as extremely low power consumption and high-d. information-processing capability. Recently, a novel ternary logic transistor has been constructed using an ultrathin ZnO/Al2O3-AlDMP/ZnO channel exhibiting a mobility edge-quantized conduction for the intermediate current level. This study investigates the operation principle of the ternary device using ZnO/Al2O3-AlDMP/ZnO stack and concludes that the first ZnO layer controls the level of the intermediate current, while the second ZnO layer controls the threshold voltage of the ternary device. These controllable elec. properties of the intermediate state of the ternary device have been applied to an n-type resistive-load std. ternary inverter, demonstrating the feasibility to achieve a ternary logic circuit consuming extremely low power with an optimal noise margin.
- 26Shim, C.-H.; Heo, S.; Noh, J.; Kim, Y. J.; Kim, S.-Y.; Khan, A. K.; Lee, B. H. Design of Ratioless Ternary Inverter Using Graphene Barristor. In 2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) ; 2016; pp 23– 30, DOI: 10.1109/ISMVL.2016.51 .There is no corresponding record for this reference.
- 27Gupta, A.; Kundu, S.; Teugels, L.; Bommels, J.; Adelmann, C.; Heylen, N.; Jamieson, G.; Pedreira, O. V.; Ciofi, I.; Chava, B.; Wilson, C. J.; Tokei, Z. High-Aspect-Ratio Ruthenium Lines for Buried Power Rail. In 2018 IEEE International Interconnect Technology Conference (IITC) ; 2018; pp 4– 6, DOI: 10.1109/IITC.2018.8430415 .There is no corresponding record for this reference.
- 28Gupta, A.; Pedreira, O. V.; Arutchelvan, G.; Zahedmanesh, H.; Devriendt, K.; Mertens, H.; Tao, Z.; Ritzenthaler, R.; Wang, S.; Radisic, D.; Kenis, K.; Teugels, L.; Sebai, F.; Lorant, C.; Jourdan, N.; Chan, B. T.; Subramanian, S.; Schleicher, F.; Hopf, T.; Peter, A. P. Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling. IEEE Trans. Electron Devices 2020, 67 (12), 5349– 5354, DOI: 10.1109/TED.2020.303351028https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB3MXht1Cmt70%253D&md5=cef09a72deab5bfef684f986e2722d8dBuried power rail integration with FinFETs for ultimate CMOS scalingGupta, Anshul; Pedreira, Olalla Varela; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, Katia; Mertens, Hans; Tao, Zheng; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, Boon Teik; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony Premkumar; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Xiuju; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Litta, Eugenio Dentoni; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, Noemie; Sepulveda, A.; Mertens, Sofie; Kim, Min-Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Christel; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano, Efrain; Mitard, Jerome; Wilson, Christopher J.; Holsteyns, Frank; Boemmels, Juergen; Demuynck, Steven; Tokei, Zsolt; Horiguchi, NaotoIEEE Transactions on Electron Devices (2020), 67 (12), 5349-5354CODEN: IETDAI; ISSN:1557-9646. (Institute of Electrical and Electronics Engineers)Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technol. requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degrdn. due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000°C, 1.5 s, without adversely impacting the stack morphol. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielec. plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high m.p. which does not diffuse into dielecs. also minimizes the risk of contamination. To assess the device degrdn., simulations are carried out showing negligible stress transfer from BPR to the channel. This is exptl. validated when no systematic difference in the dc characteristics of CMOS without BPR vs. those in close proximity to floating W-BPR lines is obsd. Addnl., the resistance of the recessed W-BPR line is measured ~ 120 ω/μm for crit. dimension (CD) ~ 32 nm and height ~ 122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330°C, making Ru a candidate for via metalization to achieve low resistance contact strategy to BPR.
- 29Kim, C.; Lee, Y.; Lee, S. Systematic Modulation of Negative-Differential Transconductance Effects for Gated P+-i-N+ Silicon Ultra-Thin Body Transistor. J. Appl. Phys. 2017, 121 (12), 124504, DOI: 10.1063/1.497921329https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC2sXlt12msLw%253D&md5=f20497b7e78bb363ce266277d997da70Systematic modulation of negative-differential transconductance effects for gated p+-i-n+ silicon ultra-thin body transistorKim, Changmin; Lee, Youngmin; Lee, SejoonJournal of Applied Physics (Melville, NY, United States) (2017), 121 (12), 124504/1-124504/4CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)The authors demonstrate the precise control of the neg.-differential transconductance (NDT) effects on a gated p+-i-n+ Si ultra-thin body transistor. The device clearly displays the N-shape transfer characteristic (i.e., NDT effect) at room temp., and the NDT behavior is fully based on the gate-modulation of the electrostatic junction characteristics. The position and the current level of the peak in the NDT region are systematically controllable when modulating the potential profile at the channel-source junction. Namely, the NDT effect can be systematically modulated through modifying the band-to-band tunneling condition by controlling both gate- and drain-bias voltages. In-depth analyses on the transport characteristics and transport mechanisms are discussed. (c) 2017 American Institute of Physics.
- 30Naquin, C.; Lee, M.; Edwards, H.; Mathur, G.; Chatterjee, T.; Maggio, K. Gate Length and Temperature Dependence of Negative Differential Transconductance in Silicon Quantum Well Metal-Oxide-Semiconductor Field-Effect Transistors. J. Appl. Phys. 2015, 118 (12), 124505, DOI: 10.1063/1.493166230https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC2MXhsFGksLbF&md5=1760dc610032668aa5d61c9e489c6da6Gate length and temperature dependence of negative differential transconductance in silicon quantum well metal-oxide-semiconductor field-effect transistorsNaquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, KenJournal of Applied Physics (Melville, NY, United States) (2015), 118 (12), 124505/1-124505/6CODEN: JAPIAU; ISSN:0021-8979. (American Institute of Physics)Introducing quantum transport into silicon transistors in a manner compatible with industrial fabrication has the potential to transform the performance horizons of large scale integrated silicon devices and circuits. Explicit quantum transport as evidenced by neg. differential transconductances (NDTCs) was obsd. in a set of quantum well (QW) transistors fabricated using industrial silicon complementary metal-oxide-semiconductor processing. Detailed gate length and temp. dependence characteristics of the NDTCs in these devices were measured. The QW potential was formed via lateral ion implantation doping on a com. 45 nm technol. node process line, and measurements of the transfer characteristics show NDTCs up to room temp. Gate length dependence of NDTCs shows a correlation of the interface channel length with the no. of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temp. dependence is consistent with partial freeze-out of carrier concn. against a degenerately doped background. (c) 2015 American Institute of Physics.
- 31Kim, K. R.; Kim, H. H.; Song, K.-W.; Huh, J. I.; Lee, J. D.; Park, B.-G. Field-Induced Interband Tunneling Effect Transistor (FITET) with Negative-Differential Transconductance and Negative-Differential Conductance. IEEE Transactions on Nanotechnology 2005, 4 (3), 317– 321, DOI: 10.1109/TNANO.2005.847008There is no corresponding record for this reference.
- 32Zhang, P.; Le, S. T.; Hou, X.; Zaslavsky, A.; Perea, D. E.; Dayeh, S. A.; Picraux, S. T. Strong Room-Temperature Negative Transconductance in an Axial Si/Ge Hetero-Nanowire Tunneling Field-Effect Transistor. Appl. Phys. Lett. 2014, 105 (6), 062106, DOI: 10.1063/1.489295032https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC2cXhtlGmtr3K&md5=11beab07176541d15cc2ce832c2a2220Strong room-temperature negative transconductance in an axial Si/Ge hetero-nanowire tunneling field-effect transistorZhang, Peng; Le, Son T.; Hou, Xiaoxiao; Zaslavsky, A.; Perea, Daniel E.; Dayeh, Shadi A.; Picraux, S. T.Applied Physics Letters (2014), 105 (6), 062106/1-062106/4CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)The authors report on room-temp. neg. transconductance (NTC) in axial Si/Ge hetero-nanowire tunneling field-effect transistors. The NTC produces a current peak-to-valley ratio >45, a high value for a Si-based device. The authors characterize the NTC over a range of gate VG and drain VD voltages, finding that NTC persists down to VD = -50 mV. The phys. mechanism responsible for the NTC is the VG-induced depletion in the p-Ge section that eventually reduces the max. elec. field that triggers the tunneling ID, as confirmed via three-dimensional (3D) technol. computer-aided design simulations. (c) 2014 American Institute of Physics.
- 33Dey, A. W.; Svensson, J.; Ek, M.; Lind, E.; Thelander, C.; Wernersson, L.-E. Combining Axial and Radial Nanowire Heterostructures: Radial Esaki Diodes and Tunnel Field-Effect Transistors. Nano Lett. 2013, 13 (12), 5919– 5924, DOI: 10.1021/nl402949433https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC3sXhslOmsLrK&md5=ff5536add353f0e68c715b4b0dba52a3Combining Axial and Radial Nanowire Heterostructures: Radial Esaki Diodes and Tunnel Field-Effect TransistorsDey, Anil W.; Svensson, Johannes; Ek, Martin; Lind, Erik; Thelander, Claes; Wernersson, Lars-ErikNano Letters (2013), 13 (12), 5919-5924CODEN: NALEFD; ISSN:1530-6984. (American Chemical Society)The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit. The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Also, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties. In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a const. drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects; however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require addnl. chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addn. to design advantages of a radial transistor architecture, the authors in this work illustrate the benefit in terms of drive current per unit chip area and compare the exptl. data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the elec. data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. The data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm2, than the max. peak current of axial GaSb/InAs-(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm2, while their axial counterparts at most carry Jpeak = 77 kA/cm2, normalized to the largest cross-sectional area of the nanowire.
- 34Ganjipour, B.; Dey, A. W.; Borg, B. M.; Ek, M.; Pistol, M.-E.; Dick, K. A.; Wernersson, L.-E.; Thelander, C. High Current Density Esaki Tunnel Diodes Based on GaSb-InAsSb Heterostructure Nanowires. Nano Lett. 2011, 11 (10), 4222– 4226, DOI: 10.1021/nl202180b34https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC3MXhtFGgtrnI&md5=9b813f5c28272b6fd50091942ce31682High Current Density Esaki Tunnel Diodes Based on GaSb-InAsSb Heterostructure NanowiresGanjipour, Bahram; Dey, Anil W.; Borg, B. Mattias; Ek, Martin; Pistol, Mats-Erik; Dick, Kimberly A.; Wernersson, Lars-Erik; Thelander, ClaesNano Letters (2011), 11 (10), 4222-4226CODEN: NALEFD; ISSN:1530-6984. (American Chemical Society)The authors present elec. characterization of broken gap GaSb-InAsSb nanowire heterojunctions. Esaki diode characteristics with max. reverse current of 1750 kA/cm2 at 0.50 V, max. peak current of 67 kA/cm2 at 0.11 V, and peak-to-valley ratio (PVR) of 2.1 were obtained at room temp. The reverse c.d. is comparable to that of state-of-the-art tunnel diodes based on heavily doped p-n junctions. However, the GaSb-InAsSb diodes studied in this work do not rely on heavy doping, which permits studies of transport mechanisms in simple transistor structures processed with high-κ gate dielecs. and top-gates. Such processing results in devices with improved PVR (3.5) and stability of the elec. properties.
- 35Carnevale, S. D.; Marginean, C.; Phillips, P. J.; Kent, T. F.; Sarwar, A. T. M. G.; Mills, M. J.; Myers, R. C. Coaxial Nanowire Resonant Tunneling Diodes from Non-Polar AlN/GaN on Silicon. Appl. Phys. Lett. 2012, 100 (14), 142115, DOI: 10.1063/1.370158635https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC38Xlt1elsbk%253D&md5=2a81369f54f45db7bf1f72e8983517d3Coaxial nanowire resonant tunneling diodes from non-polar AlN/GaN on siliconCarnevale, S. D.; Marginean, C.; Phillips, P. J.; Kent, T. F.; Sarwar, A. T. M. G.; Mills, M. J.; Myers, R. C.Applied Physics Letters (2012), 100 (14), 142115/1-142115/4CODEN: APPLAB; ISSN:0003-6951. (American Institute of Physics)Resonant tunneling diodes are formed using AlN/GaN core-shell nanowire heterostructures grown by plasma assisted MBE on n-Si(111) substrates. By a coaxial geometry, these devices take advantage of non-polar (m-plane) nanowire sidewalls. Device modeling predicts non-polar orientation should enhance resonant tunneling compared to a polar structure, and that AlN double barriers will lead to higher peak-to-valley current ratios compared to AlGaN barriers. Elec. measurements of ensembles of nanowires show neg. differential resistance appearing only at cryogenic temp. Individual nanowire measurements show neg. differential resistance at room temp. with peak c.d. of 5 × 105 A/cm2. (c) 2012 American Institute of Physics.
- 36Nourbakhsh, A.; Zubair, A.; Dresselhaus, M. S.; Palacios, T. Transport Properties of a MoS2/WSe2 Heterojunction Transistor and Its Potential for Application. Nano Lett. 2016, 16 (2), 1359– 1366, DOI: 10.1021/acs.nanolett.5b0479136https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC28XpsFaquw%253D%253D&md5=f7e8e6fb37444d520c25f84947ed6e45Transport Properties of a MoS2/WSe2 Heterojunction Transistor and Its Potential for ApplicationNourbakhsh, Amirhasan; Zubair, Ahmad; Dresselhaus, Mildred S.; Palacios, TomasNano Letters (2016), 16 (2), 1359-1366CODEN: NALEFD; ISSN:1530-6984. (American Chemical Society)This paper studies band-to-band tunneling in the transverse and lateral directions of van der Waals MoS2/WSe2 heterojunctions. We observe room-temp. neg. differential resistance (NDR) in a heterojunction diode comprised of few-layer WSe2 stacked on multilayer MoS2. The presence of NDR is attributed to the lateral band-to-band tunneling at the edge of the MoS2/WSe2 heterojunction. The backward tunneling diode shows an av. conductance slope of 75 mV/dec with a high curvature coeff. of 62 V-1. Assocd. with the tunnel-diode characteristics, a pos.-to-neg. transconductance in the MoS2/WSe2 heterojunction transistors is obsd. The transition is induced by strong interlayer coupling between the films, which results in charge d. and energy-band modulation. The sign change in transconductance is particularly useful for multivalued logic (MVL) circuits, and we therefore propose and demonstrate for the first time an MVL-inverter that shows three levels of logic using one pair of p-type transistors.
- 37Huang, M.; Li, S.; Zhang, Z.; Xiong, X.; Li, X.; Wu, Y. Multifunctional High-Performance van Der Waals Heterostructures. Nat. Nanotechnol. 2017, 12 (12), 1148– 1154, DOI: 10.1038/nnano.2017.20837https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC2sXhs1aisrrJ&md5=893ea0a9674bb9dab8d016a4a3c87658Multifunctional high-performance van der Waals heterostructuresHuang, Mingqiang; Li, Shengman; Zhang, Zhenfeng; Xiong, Xiong; Li, Xuefei; Wu, YanqingNature Nanotechnology (2017), 12 (12), 1148-1154CODEN: NNAABX; ISSN:1748-3387. (Nature Research)A range of novel two-dimensional materials have been actively explored for More Moore and More-than-Moore device applications because of their ability to form van der Waals heterostructures with unique electronic properties. However, most of the reported electronic devices exhibit insufficient control of multifunctional operations. Here, we leverage the band-structure alignment properties of narrow-bandgap black phosphorus and large-bandgap molybdenum disulfide to realize vertical heterostructures with an ultrahigh rectifying ratio approaching 106 and on-off ratio up to 107. Furthermore, we design and fabricate tunable multivalue inverters, in which the output logic state and window of the mid-logic can be controlled by specific pairs of channel length and, most importantly, by the elec. field, which shifts the band-structure alignment across the heterojunction. Finally, high gains over 150 are achieved in the inverters with optimized device geometries, showing great potential for future logic applications.
- 38Lv, W.; Fu, X.; Luo, X.; Lv, W.; Cai, J.; Zhang, B.; Wei, Z.; Liu, Z.; Zeng, Z. Multistate Logic Inverter Based on Black Phosphorus/SnSeS Heterostructure. Adv. Electron. Mater. 2019, 5 (1), 1800416, DOI: 10.1002/aelm.201800416There is no corresponding record for this reference.
- 39Xiong, X.; Kang, J.; Hu, Q.; Gu, C.; Gao, T.; Li, X.; Wu, Y. Reconfigurable Logic-in-Memory and Multilingual Artificial Synapses Based on 2D Heterostructures. Adv. Funct. Mater. 2020, 30 (11), 1909645, DOI: 10.1002/adfm.20190964539https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB3cXitFeks78%253D&md5=743da77f300c304024d1c427a5c331a0Reconfigurable logic-in-memory and multilingual artificial synapses based on 2D heterostructuresXiong, Xiong; Kang, Jiyang; Hu, Qianlan; Gu, Chengru; Gao, Tingting; Li, Xuefei; Wu, YanqingAdvanced Functional Materials (2020), 30 (11), 1909645CODEN: AFMDC6; ISSN:1616-301X. (Wiley-VCH Verlag GmbH & Co. KGaA)Nonvolatile logic devices have attracted intensive research attentions recently for energy efficiency computing, where data computing and storage can be realized in the same device structure. Various approaches have been adopted to build such devices; however, the functionality and versatility are still very limited. Here, 2-dimensional van der Waals heterostructures based on direct band gap materials black phosphorus and rhenium disulfide for the nonvolatile ternary logic operations is demonstrated for the first time with the ultrathin oxide layer from the black phosphorus serving as the charge trapping as well as band-to-band tunneling layer. Furthermore, an artificial electronic synapse based on this heterostructure is demonstrated to mimic trilingual synaptic response by changing the input base voltage. Besides, artificial neural network simulation based on the electronic synaptic arrays using the handwritten digits data sets demonstrates a high recognition accuracy of 91.3%. This work provides a path toward realizing multifunctional nonvolatile logic-in-memory applications based on novel 2D heterostructures.
- 40Dong, J.; Liu, F.; Wang, F.; Wang, J.; Li, M.; Wen, Y.; Wang, L.; Wang, G.; He, J.; Jiang, C. Configuration-Dependent Anti-Ambipolar van Der Waals p–n Heterostructures Based on Pentacene Single Crystal and MoS2. Nanoscale 2017, 9 (22), 7519– 7525, DOI: 10.1039/C7NR01822C40https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC2sXns1GrsLs%253D&md5=4bbcdeb075cb3a9276ba60b13b83fffdConfiguration-dependent anti-ambipolar van der Waals p-n heterostructures based on pentacene single crystal and MoS2Dong, Ji; Liu, Fengjing; Wang, Feng; Wang, Jiawei; Li, Molin; Wen, Yao; Wang, Liang; Wang, Gongtang; He, Jun; Jiang, ChaoNanoscale (2017), 9 (22), 7519-7525CODEN: NANOHL; ISSN:2040-3372. (Royal Society of Chemistry)Recently, van der Waals heterostructures (vdWHs) have trigged intensive interest due to their novel electronic and optoelectronic properties. The vdWHs could be achieved by stacking two dimensional layered materials (2DLMs) on top of another and vertically kept by van der Waals forces. Furthermore, org. semiconductors are also known to interact via van der Waals forces, which offer an alternative for the fabrication of org.-inorg. p-n vdWHs. However, the performances of org.-inorg. p-n vdWHs produced so far are rather poor, owing to the unmatched elec. property between the 2DLMs and org. polycryst. films. To make improvements in such novel heterostructure architectures, here we adopt high quality org. single crystals instead of polycryst. films to construct a pentacene/MoS2 p-n vdWH. The vdWHs show a much higher c.d. and better anti-ambipolar characteristics with a highest transconductance of 211 nS. Moreover, device configuration-dependent transfer characteristics are demonstrated and a mechanism of a gate bias modulated vertical space charge zone existing at the vertical p-n vdWHs interface is proposed. These findings provide a new route to optimize the org.-inorg. p-n vdWHs and a guideline for studying the intrinsic properties of vdWHs.
- 41Li, S.; Chen, X.; Liu, L.; Zeng, Z.; Chang, S.; Wang, H.; Wu, H.; Long, S.; Liu, C. Micron Channel Length ZnO Thin Film Transistors Using Bilayer Electrodes. J. Colloid Interface Sci. 2022, 622, 769– 779, DOI: 10.1016/j.jcis.2022.04.01641https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB38Xht1antL3M&md5=1e625748e86389d43a8e3f6368a23506Micron channel length ZnO thin film transistors using bilayer electrodesLi, Sizhe; Chen, Xue; Liu, Li; Zeng, Zhiyu; Chang, Sheng; Wang, Hao; Wu, Hao; Long, Shibing; Liu, ChangJournal of Colloid and Interface Science (2022), 622 (), 769-779CODEN: JCISA5; ISSN:0021-9797. (Elsevier B.V.)Micro light-emitting diodes (Micro-LEDs) are currently attracting more and more attention. Thin film transistors (TFTs) with micron channel lengths can be used to drive Micro-LEDs. The key parameters of TFTs, such as mobility, ION/IOFF and threshold voltage, still need to be improved. In this study, we propose and exptl. demonstrate ZnO TFTs using bilayer electrodes to overcome the short channel effects when the channel length is scaled down to 3μm. Ti, Mo and Sn interlayers not only serve as diffusion barriers to prohibit migration of Cu atoms from the top electrodes, but also enhance adhesive energy of the metal electrodes on ZnO channel layers. ZnO TFTs using Cu/Ti bilayer electrodes exhibit the best performance, e.g., a high mobility of 45.3 cm2V-1s-1, a high ION/IOFF ratio of 4.28 x 109, a low subthreshold of 0.24 V/dec and a proper threshold voltage of 1.13 V. The high mobility can be attributed to a significant decrease of the barrier height and a slight narrowing of the space charge layer, and the high ratio of ION/IOFF is concerned with the high electron concn. under an ON-state condition. Thus, ZnO TFTs using Cu/Ti bilayer electrodes can be used in next-generation displays.
- 42Li, H.; Han, D.; Dong, J.; Yi, Z.; Zhou, X.; Zhang, S.; Zhang, X.; Wang, Y. Enhanced Performance of Atomic Layer Deposited Thin-Film Transistors With High-Quality ZnO/Al2O3 Interface. IEEE Trans. Electron Devices 2020, 67 (2), 518– 523, DOI: 10.1109/TED.2019.295704842https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB3cXhslChsL7N&md5=82078c9e7cdbf11913133ea58488646dEnhanced performance of atomic layer deposited thin-film transistors with high-quality ZnO/Al2O3 interfaceLi, Huijin; Han, Dedong; Dong, Junchen; Yi, Zhuang; Zhou, Xiaobin; Zhang, Shengdong; Zhang, Xing; Wang, YiIEEE Transactions on Electron Devices (2020), 67 (2), 518-523CODEN: IETDAI; ISSN:1557-9646. (Institute of Electrical and Electronics Engineers)We fabricated ZnO channel/Al2O3 gate dielec. thin-film transistors (TFTs) by at. layer deposition (ALD) continuous growth process. The effects of the channel and the dielec. continuous growth on the performance of TFTs were investigated. Compared with noncontinuous growth ZnO/Al2O3 films, continuous growth ZnO/Al2O3 films with no obvious buffer layer and less residual O-H bonds possess superior ZnO/Al2O3 interface quality. The continuous growth TFTs exhibit a field-effect mobility of 19.6 cm2 V-1s-1, a subthreshold swing of 0.13 V dec-1, a high ION/IOFF of 4.1 x 109, a hysteresis window of 0.09 V, and an excellent uniformity of elec. characteristics. Continuous growth TFTs also demonstrate better stability with minor shifts of Vth 0.6 V [pos. bias stress (PBS)] and Vth - 0.3 V [neg. bias stress (NBS)]. The faster falling rates of activation energy for continuous growth TFTs indicate that the total trap d. is reduced through the continuous growth of active layer and dielec. layer. Our results suggest that the ALD-based continuous growth process could enhance the performance of TFTs.
- 43Acharya, R.; Günder, D.; Breuer, T.; Schmitz, G.; Klauk, H.; Witte, G. Stability of Organic Thin-Film Transistors Based on Ultrathin Films of Dinaphtho[2,3-b:2′,3′-f]Thieno[3,2- b]Thiophene (DNTT). Journal of Materials Chemistry C 2021, 9 (1), 270– 280, DOI: 10.1039/D0TC04554C43https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB3cXisVSks7zE&md5=253a62526f72be625ae2c3a1cb14f54bStability of organic thin-film transistors based on ultrathin films of dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT)Acharya, Rachana; Guender, Darius; Breuer, Tobias; Schmitz, Guido; Klauk, Hagen; Witte, GregorJournal of Materials Chemistry C: Materials for Optical and Electronic Devices (2021), 9 (1), 270-280CODEN: JMCCCX; ISSN:2050-7534. (Royal Society of Chemistry)Org. thin-film transistors (TFTs) based on ultrathin semiconductor films are potentially useful as highly sensitive phys., chem. or biol. sensors and may also help in the development of a better understanding of the relations between structural and charge-transport characteristics of thin films of org. semiconductors. A particularly promising small-mol. org. semiconductor is dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT). However, it was recently reported that ultrathin DNTT films spontaneously undergo dramatic morphol. changes within minutes after deposition that lead to the disaggregation of the initially closed (or at least connected) single-monolayer films into disconnected multilayer islands. Here, we investigate how this spontaneous structural reconfiguration affects the characteristics of TFTs based on ultrathin DNTT films and explore the extent to which it can be prevented by cryogenic cooling or in situ encapsulation. We fabricated inverted coplanar TFTs with a hybrid aluminum oxide/alkylphosphonic acid self-assembled monolayer gate dielec. and vacuum-deposited DNTT films with nominal thicknesses of 2.5 or 25 nm. Using at. force microscopy (AFM) we monitored the spontaneous changes in the DNTT morphol. in a quasi-continuous manner over a period of 12 h after deposition. The charge-carrier mobility of the ultrathin DNTT TFTs was found to decrease rapidly, while the mobility of the TFTs with the thicker DNTT films is far more stable. We also found that the initial closed-monolayer morphol. of the ultrathin DNTT films is preserved when the substrates are cooled to cryogenic temps. immediately after the DNTT deposition, but that the morphol. changes resume upon returning the substrates to room temp. Furthermore, we fabricated TFTs in which the ultrathin DNTT films were encapsulated in situ with a vacuum-deposited film of polytetrafluoroethylene, C60 or titanyl phthalocyanine immediately following the DNTT deposition and found that the encapsulation decelerates the structural reorganization of the ultrathin DNTT films and the concurrent degrdn. of the carrier mobility.
- 44Ibrahim, G. H.; Zschieschang, U.; Klauk, H.; Reindl, L. High-Frequency Rectifiers Based on Organic Thin-Film Transistors on Flexible Substrates. IEEE Trans. Electron Devices 2020, 67 (6), 2365– 2371, DOI: 10.1109/TED.2020.298973044https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB3cXhvFantrnK&md5=077a690b8f6ac52ec1ea14bb606d1d4eHigh-frequency rectifiers based on organic thin-film transistors on flexible substratesIbrahim, Ghada H.; Zschieschang, Ute; Klauk, Hagen; Reindl, LeonhardIEEE Transactions on Electron Devices (2020), 67 (6), 2365-2371CODEN: IETDAI; ISSN:1557-9646. (Institute of Electrical and Electronics Engineers)Rectifier circuits featuring low threshold voltages and high cutoff frequencies based on p-channel org. thin-film transistors (TFTs) have been designed, fabricated and characterized. The TFTs and circuits were fabricated by shadow-mask lithog. on flexible plastic substrates using the vacuum-deposited small-mol. org. semiconductor dinaphtho[2,3-b:2',3'-f]thieno[3,2-b] thiophene (DNTT). The TFTs have a gate dielec. with a thickness of 5.3 nm and a channel length of 10μm. The study considers the frequency characteristics of diode-connected transistors (transdiodes) and adopts circuit techniques from silicon CMOS technol., namely single-stage and multistage dynamic-threshold-compensated differential rectifiers. The characterization of the rectifier circuits indicates cutoff frequencies up to 4.75 MHz at a peak-to-peak input voltage of 3 V for transdiodes, up to 32 MHz at a peak-to-peak input voltage of 1.5 V for single-stage differential rectifiers and up to 7.5 MHz at a peak-to-peak input voltage of 1.5 V for two-stage rectifiers. The efficiency is 25% for a load of 10 MΩ and below 1% for a load of 1 MΩ.
- 45Kobashi, K.; Hayakawa, R.; Chikyow, T.; Wakayama, Y. Negative Differential Resistance Transistor with Organic P-n Heterojunction. Adv. Electron. Mater. 2017, 3 (8), 1700106, DOI: 10.1002/aelm.201700106There is no corresponding record for this reference.
- 46On, S.; Kim, Y.-J.; Lee, H.-K.; Yoo, H. Ambipolar and Anti-Ambipolar Thin-Film Transistors from Edge-on Small-Molecule Heterostructures. Appl. Surf. Sci. 2021, 542, 148616, DOI: 10.1016/j.apsusc.2020.14861646https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BB3cXisFyqs7nE&md5=fac3852dd0610f8fd4e66f2f6545e8abAmbipolar and anti-ambipolar thin-film transistors from edge-on small-molecule heterostructuresOn, Sungmin; Kim, Young-Joon; Lee, Han-Koo; Yoo, HocheonApplied Surface Science (2021), 542 (), 148616CODEN: ASUSEE; ISSN:0169-4332. (Elsevier B.V.)Heterostructure electronic devices potentially provide opportunities for novel transistor operations, including ambipolar and anti-ambipolar switching characteristics. However, there are still no previous studies investigating the phys., chem., and morphol. properties of small-mol. semiconductor films deposited as heterojunctions. Here, we systemically investigate chem. and morphol. structure in a heterostructure of small-mol. org. semiconductors using XPS, near-edge X-ray absorption of fine structure (NEXAFS), and UPS (UPS). The anal. reveals that dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) and N,N'-ditridecylperylenediimide (PTCDI-C13) maintain their chem. compns., energy structure, and edge-on mol. orientations (tilt angle = 66°). Furthermore, ambipolar and anti-ambipolar transistors are demonstrated using the edge-on DNTT/PTCDI-C13 heterostructure. These transistors enable CMOS-like inverter and ternary inverter operations as resp. example applications of ambipolar and anti-ambipolar transistors.
- 47Nakata, M.; Tsuji, H.; Sato, H.; Nakajima, Y.; Fujisaki, Y.; Takei, T.; Yamamoto, T.; Fujikake, H. Influence of Oxide Semiconductor Thickness on TFT Characteristics. 2012 19th International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD) ; 2012.There is no corresponding record for this reference.
- 48Chang, J.-F.; Shie, H.-S.; Yang, Y.-W.; Wang, C.-H. Study on Correlation between Structural and Electronic Properties of Fluorinated Oligothiophenes Transistors by Controlling Film Thickness. Crystals 2019, 9 (3), 144, DOI: 10.3390/cryst903014448https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC1MXovV2nsbc%253D&md5=3c885f2028c21db625d975f022d61a35Study on correlation between structural and electronic properties of fluorinated oligothiophenes transistors by controlling film thicknessChang, Jui-Fen; Shie, Hua-Shiuan; Yang, Yaw-Wen; Wang, Chia-HsinCrystals (2019), 9 (3), 144/1-144/14CODEN: CRYSBC; ISSN:2073-4352. (MDPI AG)α,ω-Diperfluorohexylquaterthiophene (DFH-4T) has been an attractive n-type material employed in the development of high-mobility org. field-effect transistors. This paper presents a systematic study of the relationship between DFH-4T transistor performance and film structure properties as controlled by deposited thickness. When the DFH-4T thickness increases from 8 nm to 80 nm, the room-temp. field-effect mobility increases monotonically from 0.01 to 1 cm2·V-1·s-1, while the threshold voltage shows a different trend of first decrease then increase. The morphol. of thin films revealed by at. force microscopy shows a dramatic change from multilayered terrace to stacked rod like structures as the film thickness is increased. Yet the crystallite structure and the orientation of mol. constituent, as detd. by X-ray diffraction and near-edge X-ray absorption fine structure resp., do not differ much with respect to film thickness increase. Further analyses of low-temp. transport measurements with mobility-edge model demonstrate that the electronic states of DFH-4T transistors are mainly detd. by the film continuity and crystallinity of the bottom multilayered terrace. Moreover, the capacitance-voltage measurements of DFH-4T metal-insulator-semiconductor diodes demonstrate a morphol. dependence of charge injection from top contacts, which well explains the variation of threshold voltage with thickness. The overall study provides a deeper understanding of microstructural and mol. growth of DFH-4T film and clarify the structural effects on charge transport and injection for implementation of high-mobility top-contact transistors.
- 49Lovie, P. Coefficient of Variation. Encyclopedia of Statistics in Behavioral Science; John Wiley & Sons, Ltd.: Chichester, 2005; Vol. 1, pp 317– 318, DOI: 10.1002/0470013192.bsa107 .There is no corresponding record for this reference.
- 50Stanford University CNTFET Model, https://nano.stanford.edu/downloads/stanford-cnfet-model (accessed Feb 14, 2022).There is no corresponding record for this reference.
- 51Predictive Technology Model (PTM), http://ptm.asu.edu (accessed Feb 14, 2022).There is no corresponding record for this reference.
- 52Etiemble, D. Comparing Ternary and Binary Adders and Multipliers. 2019, arXiv:1908.07299, https://arxiv.org/abs/1908.07299 (accessed Feb 8, 2022).There is no corresponding record for this reference.
- 53Lee, S.; Striakhilev, D.; Jeon, S.; Nathan, A. Unified Analytic Model for Current–Voltage Behavior in Amorphous Oxide Semiconductor TFTs. IEEE Electron Device Lett. 2014, 35 (1), 84– 86, DOI: 10.1109/LED.2013.229053253https://chemport.cas.org/services/resolver?origin=ACS&resolution=options&coi=1%3ACAS%3A528%3ADC%252BC2cXjtlWlsLg%253D&md5=1e4149e52f481aff0f05012c36e8bbf6Unified analytic model for current-voltage behavior in amorphous oxide semiconductor TFTsLee, Sungsik; Striakhilev, Denis; Jeon, Sanghun; Nathan, ArokiaIEEE Electron Device Letters (2014), 35 (1), 84-86CODEN: EDLEDZ; ISSN:0741-3106. (Institute of Electrical and Electronics Engineers)We present a simple and semi-phys. anal. description of the current-voltage characteristics of amorphous oxide semiconductor thin-film transistors in the above-threshold and sub-threshold regions. Both regions are described by single unified expression that employs the same set of model parameter values directly extd. from measured terminal characteristics. The model accurately reproduces measured characteristics of amorphous semiconductor thin film transistors in general, yielding a scatter of <4%.
Supporting Information
Supporting Information
The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsnano.2c03523.
Fabrication process flow of the ZnO–DNTT AAS device, XPS analysis of ZnO and DNTT, transfer curves and transconductance of ZnO–DNTT AAS device dependence on voltage bias, transfer curves of ZnO and DNTT single TFT dependence on channel thickness and doping type, various STI schemes, comparison of STI operation, various ternary circuit designs and their operation (Figures S1–S9) and PM ternary device switching table (Table S1) (PDF)
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