Electrical Control of Uniformity in Quantum Dot Devices

Highly uniform quantum systems are essential for the practical implementation of scalable quantum processors. While quantum dot spin qubits based on semiconductor technology are a promising platform for large-scale quantum computing, their small size makes them particularly sensitive to their local environment. Here, we present a method to electrically obtain a high degree of uniformity in the intrinsic potential landscape using hysteretic shifts of the gate voltage characteristics. We demonstrate the tuning of pinch-off voltages in quantum dot devices over hundreds of millivolts that then remain stable at least for hours. Applying our method, we homogenize the pinch-off voltages of the plunger gates in a linear array for four quantum dots, reducing the spread in pinch-off voltages by one order of magnitude. This work provides a new tool for the tuning of quantum dot devices and offers new perspectives for the implementation of scalable spin qubit arrays.

Variations, in particular at the nanoscale, may lead to significant alterations of the relevant device metrics [1,2,21], such as the voltage needed to load a single electron to be used as a spin qubit.These variations can complicate the tuning of initialization, control or readout and potentially form a roadblock for larger systems.Additionally, qubit-to-qubit variability may require the use of individual control electronics for each qubit, as is common practice in current experimental implementations, thus challenging the scalability.While several proposals have been put forward to scale quantum dot qubits [2,[22][23][24], in all cases a high level of device uniformity is critical in their realization.
For semiconductor quantum dot qubits, the uniformity of the potential landscape is the key parameter that dictates the number of control voltages required per qubit.Ideally, a few voltages would suffice to induce a highly regular potential landscape as drawn in Fig. 1.b.Yet, potential fluctuations are naturally present as illustrated in Fig. 1.c.They can be caused by defects and charge traps, mechanical stress induced by the deposition of metallic gates [25,26], as well as variations in material growth or in the exact shape of the gates.The development of devices based on quantum wells buried in heterostructures, similar to that sketched in Fig. 1.a, already has led to a drastic improvement of the uniformity compared to metal-oxide-semiconductor systems [27].This has enabled the control of up to 16 quantum dots in a fourby-four array with shared gate control [28].However, significant variations in the quantum dot potential landscape are still commonly observed [28][29][30].This raises the question whether material [4] and fabrication development [20,28,31,32] will suffice to reach the required uniformity to operate large qubit arrays.
Here, we present an alternative method and demonstrate electrical control of quantum dot uniformity.Our approach takes advantage of the gate voltage hysteresis, an ubiquitous effect observed in semiconductor heterostructures, that is mostly considered as a limitation in the tune-up of quantum dots.It manifests in shifts of the gate voltage characteristics and is commonly explained by a build up of charges at the interface between the semiconductor barrier and the dielectrics which then alter the electric field in the buried quantum well [33][34][35][36][37][38][39].We unveil the hysteresis and its effects on the potential landscape beneath the gates by studying how pinchoff characteristics evolve with the application of tailored stress voltage sequences.This method allows us to tune those pinch-off voltages over hundreds of millivolts after which they remain stable at least on the time scale of hours.We then apply our findings to homogeneize the plunger gate pinch-off characteristics in a linear quantum dot array reducing potential fluctuations in the quantum well underneath the corresponding gates.
The gate voltage required to confine a single electron or hole typically varies between quantum dots in an array as it is dependent on the local electrostatic environment.These fluctuations also affect the pinch-off curve as exemplary depicted for sweeping the four plunger gates of a linear quantum dot device (similar to that shown in Gate voltage V g (V)

Ideal devices b c d a
Figure 1.Fluctuations in the potential landscape in semiconductor quantum dot devices.a, Schematics of typical semiconductor heterostructures with buried quantum wells studied.The metallic gate electrodes colored in blue and yellow represent the barrier (B) and plunger gates (P) of a quantum dot array, respectively.b, Potential landscape in an ideal device with shared gate control.The application of the same voltage V P/B on all plunger/barrier gates leads to a regular potential landscape with fluctuations negligible compared to those of the other relevant energy scales (α denotes the gate lever arm).
The quantum dots all have the same charge configuration.c, Potential landscape in state of the art devices with shared gate control.The application of the same voltage V P/B on all plunger/barrier gates leads to an irregular potential landscape due to local fluctuations which are often comparable or larger than the charging energy E C .Consequently, the quantum dots have different charge configurations.d, Typical variations in the pinch-off characteristic of the plunger gates in a state-of-the-art linear quantum dot array (device A), nominally identical to the one displayed in in Fig. 4.a, just after a cooldown.The pinch-off voltage V thres is defined as the gate voltage for which the current reaches I thres = 50 pA at a bias of |V sd | = 100 µV.Here, the pinch-off voltages spread over a voltage range ∆V thres = 225 mV.defined quantum dot.Therefore, we will employ pinchoff characteristics in the following to efficiently estimate variations in the potential landscape on the length scale of single quantum dots.In particular, we focus on the pinch-off voltages V thres defined as the gate voltages at which a current of I thres = 50 pA is reached for an applied source drain bias of |V sd | = 100 µV.
We study devices in 28 Si/SiGe heterostructures [40] and investigate how the pinch-off voltage of a single gate evolves depending on the previously applied gate voltages.To that end, we conduct systematic transport measurements at 4.2 K similar to sequences in [41][42][43][44] following the procedure depicted in Fig. 2.a.First a stress voltage V stress is applied to the gate under study for a time t stress = 1 min.Then the gate-voltage is swept back until the pinch-off condition I = I thres is met.This sequence is repeated several times with evolving stress voltages to measure the evolution of V thres as a function of V stress .First, the applied stress voltage V stress is decreased stepwise to be increased gradually again (not illustrated) after reaching a reversal point V stress = V rev stress .Fig. 2.b shows the resulting pinch-off voltage evolution for a plunger gate P i that is part of a linear quantum dot array for two different cooldowns (light blue and dark blue curve, respectively).In these cases, V stress is first lowered step-wise from V stress = 1.05 V to V rev stress = −3.7 V. We observe that up to V stress > −2.0 V the pinch-off voltages V thres stay within ±15 mV of the first pinch-off voltage V 0 thres = 1.06 V forming a plateau.Then, they drop down rapidly to V thres = 0.83 V.At V rev stress = −3.7 V, the sweep direction is reversed and we start to increase V stress progressively.However, we do not observe a reversed behavior.Instead, from V stress = −2.7 V to V stress = 0.9 V, the pinch-off voltages increase by less than 25 mV forming a second plateau.Only when V stress = 1.0(1.1)V for the first(second) cooldown, V thres starts to increase steeply again.The ensembles of (V stress ,V thres ) values draw typical hysteresis cycles with plateaus marking the ranges of applicable gate voltages over which the pinch-off voltage is not significantly changing.Furthermore, Fig. 2.b highlights the effect of thermal cycling on these measurements and reveals a remarkable overlap of the hysteresis cycles measured during two different cooldowns.A high degree of similarity is also observed when comparing successive measurements performed using the same stress voltage sequence as shown in supplementary Fig. S2 for gate S of device D. This suggests that the underlying process has a deterministic nature.
Similar experiments performed on another sample with varying reversal points V rev stress result in the cycles plotted in Fig. 2.c.The shape of the curves is nearly identical for each iteration.Again, we observe plateaus where the pinch-off voltage deviates by less than 50 mV from its first value.Yet, the position of the plateaus varies with the chosen V rev stress .The pinch-off voltage plateaus can be shifted by up to |∆V thres | = 290 mV for the lower plateau and by up to |∆V thres | = 400 mV for the upper one.Overall, Fig. 2.b and Fig. 2.c suggest that by applying a dedicated voltage sequence the pinch-off voltage can be adjusted on-demand to chosen targets and thus that the intrinsic potential landscape underneath the gates can be tuned.
We also note that similar hysteretic behaviours, with Gate voltage Vstress is first decreased before being increased again after Vstress = 3.7 V.Both sets of points draw hysteresis cycles which overlap.The remaining gates that are needed to form a conductive channel are set to V0 = 1.2 V. c, (Vstress,V thres ) hysteresis cycles measured successively for plunger gate P1 in device A. The points where the stress voltage sequences are reversed (star) and ended (circle) are changed between each cycle.Note that for the fifth iteration, the stress voltage sequence with increasing Vstress was stopped purposely when V thres 1 V.All other gates are set to V0 = 1.704V.
sample-dependent variations of the exact shape of the (V stress ,V thres ) curves, are consistently found in several Si/SiGe devices (e.g.device D gate S shown in supplementary Fig. S2) as well as in samples made from Ge/SiGe heterostructures (see supplementary Fig. S3) suggesting a common underlying mechanism.The observed reproducibility and the large control window of the pinch-off voltage are the foundations of our approach to homogenize the potential landscape below an ensemble of gates.
However, the electrical tuning of the intrinsic potential uniformity is of practical interest only if the resulting potential landscape remains stable afterwards.Therefore, we study how the pinch-off voltage evolves in time after stopping the hysteresis measurement cycle at varying points (see supplementary section I.C for the detailed experimental procedure).Fig. 3.a shows the time evolution directly after the application of decreasing (pink/violet) and increasing (orange) stress voltages.For comparison, we also plot how the pinch-off voltage evolves right after a cooldown without prior application of a stress voltage sequence (blue).For decreasing V stress sequences, the pinch-off voltages converge into steady states after initial decays and the time evolution exhibits random abrupt jumps.For the situation where no stress voltage or increasing stress voltages V stress are applied no significant variations of V thres are observed.The relative evolution depicted in Fig. 3.b reveals that for t > 2 hours, the voltage fluctuations are similar for all three situations.This is confirmed by extracting the standard deviations of V thres for experiments with and without application of stress voltage sequence which are σ stress = 0.4 mV (orange), σ stress = 1.0 mV (pink and violet) and σ no stress = 0.8 mV (blue), respectively.These experiments suggest that after a potential initial transient regime there is no change in the stability of the device due to the electrical tuning.This stability is observed for at least one hour and up to three depending on the voltage sequence applied.
Next we apply our findings and probe the capability to homogenize the pinch-off voltages V i thres of a group of plunger gates P i with i in [1,4] in a quantum dot array.Fig 4.a displays the device studied which has a geometry similar to linear quantum dot arrays in ref. [12,15,29,45].The pinch-off characteristics recorded prioir to the tuning sequence are depicted in the left panel of Fig 4.c and show a spread ∆V thres = max(V thres ) − min(V thres ) of 153 mV.Employing increasing gate voltage stress we tune the individual plunger pinch-off voltages to a target value V target = 1.05 V chosen before starting the tuning.Fig. 4.b illustrates the procedure followed for the specific case of two gates.V stress is gradually increased in steps n.For each V n stress , the plunger gates are sequentially stressed, measured and parked ∆V park = 50 mV above their latest pinch-off voltage where they remain until the next stress voltage V n+1 stress = V n stress + ∆V stress is selected.When a pinch-off voltage V i thres crosses the target voltage V target the corresponding plunger gate P i is henceforth not stressed anymore.A full automated round of this sequence finishes after all pinch-off voltages are larger than the target voltage.The complete procedure is repeated two times with a stress voltage resolution of ∆V stress = 25 mV taking approximately 9 hours in total.All applied stress voltages and measured pinch-off voltages are visualized in the panels of Fig. 4.d.After each repetition a pinch-off characterization is performed with the resulting curves depicted in Fig. 4.c.During the first round the pinch-off voltages shift towards the target voltage V target (indicated by the red dashed line) finally spreading in a range of ∆V thres = 86 mV around it.This spread is further reduced by the following iteration reaching a final value of ∆V thres = 20 mV.Afterwards the plunger pinch-off characteristics are observed to remain stable at least for 20 minutes (see supplementary Fig. S4).
To put this result into context, we compare the final spread of pinch-off voltages to the degree of uniformity needed to load an array of quantum dots with a single electron at each site using a single common gate voltage.This would require the potential fluctuations below the gates to be smaller than the average charging voltage that is needed to alter the charge occupation, with E C the charging energy and α the gate lever arm.This charging voltage typically ranges from 10 to 60 mV in devices similar to that under study [27,29,45,46].Assuming that pinch-off voltages constitute a witness of the intrinsic potential landscape in the quantum well, the final spread ∆V thres = 20 mV reached after electrical tuning promises a path towards the homogenization of quantum dot potentials inside an array.Even smaller spreads might be achievable by decreasing the stress voltage resolution ∆V stress .We envision that a similar method could be used to tune the potential underneath all plunger and all barrier gates simultaneously.It could allow to also equalize the inter-dot tunnel couplings and to reach an energy landscape similar to that in Fig. 1.b.
At the same time, optimization of the automated procedure could lead to a significant increase of the tuning efficiency.Such an optimized procedure may be obtained by dividing the tuning into coarse and fine steps and exploring different stressing times and thereby could drastically reduce the tuning time.Additionally, utilizing a model to predict the effect of the next stress voltage, could further minimize the number of steps required to reach the target potentials and simultaneous tuning of multiple gates may be envisioned in larger quantum dot arrays.
Adapted tuning procedures may also be designed for scalable device architectures.In a crossbar gate architecture [24,28], one could envision to apply different stressing voltages on different sets of gates such that only close to the crossing points of these gates the combined electric field is strong enough to shift the intrinsic potential.This would allow parallel but individual stressing of selected sites in a row-by-row manner.Another degree of selectivity might be provided through biasing of purposely isolated parts of the quantum well.Effectively, this would locally change the gates' reference potential and thereby locally alter the effect of the stressing voltages applied to them.Further work is needed to confirm the viability of these approaches.
Also, a better understanding of the underlying mechanism of the hysteresis would be valuable to exploit it most efficiently.A possible origin might be the trapping and detrapping of charge in or close to the dielectric capping layer caused by the application of stress voltages [33][34][35][36][37][38].For example, a positive stress voltage might enable the tunnelling of electrons from the quantum well or traps underneath non-stressed gates to traps underneath the stressed gate.These traps could be bound states in the non-oxidized part of the silicon capping layer or at its SiGe interface.They can be induced by charge defects in the gate oxide [47] or emerge due to mechanical stress originating from the deposition of metallic gates [25,26].Also, charge trapping into and out of of unpassivated silicon and germanium dangling bonds [48][49][50], charge trapping in the oxide itself mediated by leakage currents [44,[51][52][53] or movement of mobile ions [54] might be underlying the hysteresis.In all cases, when the gate voltage stress is removed the charges would be expected to be immobile at the device operation temperature and would cause local shifts in the intrinsic potential landscape observable as alterations in the pinch-off characteristics.This tunneling and trapping of charge also would be highly similar to the principle used to operate modern flash memories (based on electrically erasable programmable read only memories) which encode their stored information in pinch-off voltages and rely on gate stacks specifically engineered for that purpose [53,55].They could inspire new heterostructures and gate stacks  Pinch-off voltage V thres (V) a, Scanning electron micrograph of a linear quantum dot array.The plunger, barrier, accumulation and screening gates are colored in blue, yellow, orange and violet, respectively.The current flow is depicted by the dashed line.We aim at equalizing the pinch-off voltages of the plunger gates Pi. b, Schematics of the strategy followed illustrated with only two gates for clarity.Note that here, in contrast to the illustration in Fig. 2.A, the pinch-off voltage V thres is detected through lowering the gate voltage until I = I thres .c, Evolution of the pinch-off characteristics in device A after two iterations of the tuning procedure.The target voltage Vtarget = 1.05 V is marked by a red dashed line.After two iterations the spread of the pinch-off voltage ∆V thres is reduced from 153 mV to 20 mV.d, Evolution of V thres for each gate while Vstress is increased during the tuning procedure.The red dashed line indicates the target pinch-off voltage Vtarget = 1.05 V.The stressing on each gate is stopped when its pinch-off voltage becomes larger than Vtarget.The coloring of the data points encodes the time evolution of the stress and pinch-off voltages of the gates during each iteration.
with dedicated trapping layers further refining the tunability of the potential landscape using the gate voltage hysteresis.
In conclusion, we have presented a new method to increase the electrostatic potential uniformity in quantum dot devices electrically.We show that we can take advantage of hysteric shifts in gate voltage characteristics to deliberately tune pinch-off voltages across a wide range of more than 500 mV by applying stress voltage sequences.The resulting states remain stable on the time scale of hours.Utilizing our method, we have shifted and equalized the pinch-off voltages of four plunger gates in a linear quantum dot array to a predetermined target voltage.Although most of our results were obtained in Si/SiGe heterostructures other measurements indicate that the effect and method also can be used in other heterostructure materials like Ge/SiGe.Our work opens up a new path to increase uniformity in quantum dot based spin qubits.It may enable reducing overheads in tuning and control making the implementation of scalable architectures more feasible in practise.valuable advices.We also acknowledge S. Philips for his help on the Si/SiGe device designing.We thank L.M.K Vandersypen for his feedback as well as all the members of the Veldhorst and Vandersypen group for stimulating discussions.We thank J. D. Mensingh and N. P. Alberts for their technical support with the experimental set-ups and S. L. de Snoo for software support.
We acknowledge support through an ERC Starting Grant and through an NWO projectruimte.This research was supported by the European Union's Horizon 2020 research and innovation programme under the Grant Agreement No. 951852 (QLSI project).Research was sponsored by the Army Research Office (ARO) and was accomplished under Grant No. W911NF-17-1-0274.The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the Army Research Office (ARO), or the U.S. Government.The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation herein.
which shows a single quantum dot aimed to be a single electron transistor.It is located at the corner of a larger 3×3 quantum dot array (not shown here).

III. REPRODUCIBILITY OF THE (V thres ,Vstress) HYSTERESIS CYCLES
To provide further evidence of the reproducibility of the hysteresis cycles, we perform an experiment where the same sequences of decreasing and then increasing stress voltages are repeated ten times for gate S in device D. To reduce the measurement time, we focus mostly on the voltage range where V thres shows a strong evolution with V stress .The results are displayed in Fig. S2.We recognize the left and right flanks of the hysteresis cycles as well as the end of the V thres plateaus for decreasing V stress .Remarkably, the data obtained for the ten iterations collapse onto single curves both for increasing and decreasing V stress .This further illustrates the high reproducibility of the (V thres ,V stress ) hysteresis cycle that can be achieved.
followed in Fig. 2.These measurements are performed at base temperature of a dilution refrigerator and an estimated electron temperature of approximately 140 mK [3] and the pinch-off voltage was defined as the voltage at which the current reaches I thres = 500 pA at an source drain bias of |V sd | = 100 µV.Overall, we observe similar features to those observed in the Si/SiGe devices i.e. overlapping hysteresis cycles with a tunable voltage range of a few hundred millivolts.These measurements highlight that the hysteresis of the pinch-off voltages is observable in multiple semiconductor heterostructures and that the tuning method presented in this work may be used in different materials as well.

V. STABILITY OF THE PINCH-OFF CHARACTERISTICS AFTER TUNING THEM USING THE HYSTERETIC BEHAVIOUR
Here, we discuss the stability of pinch-off voltages after reduction of their spread using the protocol presented in Fig. 4. Fig. S4 shows the pinch-off characteristics right after, 6, and 21 minutes after the tuning.For each plunger gate considered, the three plots virtually overlap perfectly suggesting a high degree of stability.This also is in agreement with the absence of variations observed in the time stability measured after application of increasing stress voltages in Fig. 3.It supports our choice of using increasing stress voltages in the tuning procedure presented.T2 provide an overview of the different samples underlying the figures in this work, their gate design, the gates that were swept, and the reversal points V rev stress after which the stress voltage sequence was reversed if applicable.The gate designs and gate names mentioned in Table T1 can be found in supplementary Fig. S1.Supplementary Fig. S3 shows gate designs and gate names for the SHTs referred to in Table T2.

Table T1 and Table
Fig 4.a) in Fig. 1.d.The curves reveal the local depletion of a conducting path through the quantum well and experimentally can be obtained in a very short time compared to the time required for the formation of a well

Figure 2 .
Figure 2. Hysteresis of the pinch-off characteristics.a, Schematics of the measurement sequence used to probe the hysteretic behavior of the pinch-off voltage V thres of a single gate.V thres , i.e. the voltage when the current reaches I thres = 50 pA at a bias voltage |V sd | = 100 µV, is measured after application of successive stress voltages Vstress for tstress = 1 min.b, Evolution of the pinch-off voltage V thres of the sensor plunger gate S as a function of the stress voltage Vstress for two different cooldowns of device B. The measurement cycle is sketched in the top illustration.The square and the circle mark the starting point and the ending point of the cycles, respectively.The star indicates the point V revstress where the stress voltage sequence is reversed.Vstress is first decreased before being increased again after Vstress = 3.7 V.Both sets of points draw hysteresis cycles which overlap.The remaining gates that are needed to form a conductive channel are set to V0 = 1.2 V. c, (Vstress,V thres ) hysteresis cycles measured successively for plunger gate P1 in device A. The points where the stress voltage sequences are reversed (star) and ended (circle) are changed between each cycle.Note that for the fifth iteration, the stress voltage sequence with increasing

Figure 3 .
Figure3.Stability of the pinch-off voltage after tuning.a, Time evolution of the V thres prior to any application of stress voltages blue) and after tuning via application of increasing Vstress with V rev stress > 0 V (orange) or decreasing Vstress with V rev stress < 0 V (pink and violet).The curves are obtained for sensor plunger gate S in device C, except of the pink curve which is obtained for sensor plunger gate S in device D. b, Relative variations ∆V thres = V thres (t) − V thres (t = 3 h) of the data shown in a.

Figure 4 .
Figure 4. Homogenization of the potential landscape below the plunger gates of a linear quantum dot array.a, Scanning electron micrograph of a linear quantum dot array.The plunger, barrier, accumulation and screening gates are colored in blue, yellow, orange and violet, respectively.The current flow is depicted by the dashed line.We aim at equalizing the pinch-off voltages of the plunger gates Pi. b, Schematics of the strategy followed illustrated with only two gates for clarity.Note that here, in contrast to the illustration in Fig.2.A, the pinch-off voltage V thres is detected through lowering the gate voltage until I = I thres .c, Evolution of the pinch-off characteristics in device A after two iterations of the tuning procedure.The target voltage Vtarget = 1.05 V is marked by a red dashed line.After two iterations the spread of the pinch-off voltage ∆V thres is reduced from 153 mV to 20 mV.d, Evolution of V thres for each gate while Vstress is increased during the tuning procedure.The red dashed line indicates the target pinch-off voltage Vtarget = 1.05 V.The stressing on each gate is stopped when its pinch-off voltage becomes larger than Vtarget.The coloring of the data points encodes the time evolution of the stress and pinch-off voltages of the gates during each iteration.

Figure S1 .
Figure S1.Scanning electron micrograph of Si/SiGe devices studied.a, Linear four quantum dot array, b, Single electron transistor at the edge of a 3×3 quantum dot array.The plunger gates are colored in yellow, the barrier gates in blue, the accumulation gates in orange and the screening gates in violet.In a, the plunger gates belonging to the linear channel are labelled Pi whereas that of the charge sensors are labelled Si.In b, the plunger gate of the sensor used during the experiments is labelled S.

Figure S2 .
Figure S2.Overlap of multiple hysteresis cycles.Evolution of V thres as a function of Vstress for 10 successive cycles obtained for gate S in device D. A schematic of the stress voltage sequence applied during one iteration is sketched on the right.The square and the circle mark the starting point and the ending point of the cycles, respectively.The star indicates the point where the stress voltage direction is reversed.The V thres plateaus are not measured or only partially (grey dashed lines).All the curves collapse onto each other showing a remarkable reproducibility.

Figure S4 .
Figure S4.Stability of the plunger gate pinch-off characteristics after tuning them to the target voltage.Pinch-off characteristics measured just after (plain lines), 6 minutes (dotted lines) and 21 minutes (dashed lines) after the homogeneization procedure described in the main text using the hysteretic shift.The red dashed line marks the target voltage of the tuning.

Figure
FigureDeviceType of Gate(s) Cycle number Reversal/end point(s) V