Single-Electron Occupation in Quantum Dot Arrays at Selectable Plunger Gate Voltage

The small footprint of semiconductor qubits is favorable for scalable quantum computing. However, their size also makes them sensitive to their local environment and variations in the gate structure. Currently, each device requires tailored gate voltages to confine a single charge per quantum dot, clearly challenging scalability. Here, we tune these gate voltages and equalize them solely through the temporary application of stress voltages. In a double quantum dot, we reach a stable (1,1) charge state at identical and predetermined plunger gate voltage and for various interdot couplings. Applying our findings, we tune a 2 × 2 quadruple quantum dot such that the (1,1,1,1) charge state is reached when all plunger gates are set to 1 V. The ability to define required gate voltages may relax requirements on control electronics and operations for spin qubit devices, providing means to advance quantum hardware.


INTRODUCTION
Semiconductor spin qubits have become a compelling platform for quantum computation.Single qubit gate fidelities of 99.99% [1] and two-qubit gate fidelities exceeding 99% [2][3][4][5] have been demonstrated.A moderate sensitivity to thermal effects allowed for the implementation of quantum operations above one Kelvin [6][7][8].Furthermore, the small size of semiconductor spin qubits and their compatibility with advanced semiconductor manufacturing [9][10][11] may facilitate devices with large numbers of qubits as required for practical applications.Recent advances in the material platforms supported the realization of a 2 × 2 qubit array in germanium [12], a linear six qubit system in silicon [13], and the operation of a 16 quantum dot crossbar array [14].However, scaling up the number of qubits is challenging, especially when considering the numbers needed for fault-tolerant quantum computation [15][16][17].A particular challenge lies in the sensitivity of qubits to their environment leading to considerable variations of their properties, a notion that was already highlighted in the seminal work on quantum computation by Loss and DiVincenzo [18].
Substantial reductions in variability have been achieved through progress in heterostructure growth and device fabrication.For instance, these efforts focus on reducing material disorder [19][20][21][22][23][24][25][26], advancing device fabrication [27][28][29] and addressing fluctuations in mechanical stress induced by the deposition of metallic gate electrodes [30][31][32].However, significant variations remain observable in current devices [14,33,34] and it is an open question whether sufficient uniformity can be reached through material development alone.* corresponding author: m.veldhorst@tudelft.nl Alternatively, fluctuations in the potential landscape can be compensated by temporarily applying stress voltages [35][36][37][38].An alternating sequence of stress voltages and pinch-off measurements has already enabled ondemand reshaping of pinch-off voltage characteristics and their homogenization without signs of reduced device stability afterwards.Furthermore, such sequences allowed to alter the potential offset of a single electron transistor (SET) at a temperature of ≈ 4.2 K [38].Yet, this methodology has not been applied to individual electrons in a quantum dot.Also, overcoming qubit variations in quantum processors will require the tuning of multiple quantum dots.
Here, we demonstrate the use of stress voltages to tune the potential landscape in a quantum dot array.We show that this approach allows to change and equalize the plunger gate voltages required to reach single-electron occupation in a double quantum dot without changing any other gate voltages.Importantly, we find that the resulting confining potential remains stable for hours afterwards.To illustrate its robustness and versatility, we demonstrate that the method employed can be applied at various barrier voltages and thus interdot tunnel couplings.Furthermore, we show that the procedure can be extended to homogenize the plunger gate voltages defining the single occupation charge state in a 2 × 2 quantum dot system.

RESULTS
Fig. 1.a shows a scanning electron micrograph of a device nominally identical to the one under study in this work, which is fabricated on a 28 Si/SiGe heterostructure [39] (see methods).The gate design allows for the formation of a 2 × 2 quantum dot array (white circles) and two adjacent single electron transistors (SETs) on the left and right side [40].We form the quantum dots Q3 and Q4 underneath the plunger gates P3 and P4 and also tune up the SET below the sensor gate S1.The left side of the device is operated as an electron reservoir.Pi , V + Pi ] from the first to the second charge transition line of the two quantum dots are indicated by a horizontal and a verti-cal bar (see methods for the definition).As illustrated in Fig. 1.c those ranges do not overlap for the two quantum dots and in particular we find a separation of more than 2(4) times the Q3(Q4) charging voltage While this is a rather extreme case, significant asymmetries of the plunger gate voltage ranges loading a single electron are commonly observed in quantum dot devices [14,33,[41][42][43].Therefore, if single-electron occupation can be achieved at equal plunger gate voltages in the device of Fig. 1 this would provide good prospects for the homogenization of the required plunger gate voltages in other devices that already are intrinsically more uniform.

(1,1) charge occupation at predetermined plunger gate voltage
To increase the potential uniformity, we follow our previous work [38] and apply stress voltages V stress on gate electrodes to reshape the background potential landscape.We aim to tune the system such that the (1,1) charge state is reached at predetermined plunger gate voltage.Specifically we target to load a single electron per quantum dot for V P3 = V P4 = V T with V T = 1 V, 1.1 V and 1.2 V by sequentially tuning the potential below the two plunger gates following the path shown in Fig. 2.b.Fig. 2.a illustrates the employed procedure for a single plunger gate Pi.We apply a stress voltage V stress for t stress = 1 min.Afterwards, we measure charge stability diagrams around V Pi = V T and if necessary the sensor gate voltage V S1 is compensated to restore maximum sensitivity of the SET.From the charge stability diagrams we then extract the voltage range [V − Pi , V + Pi ] required to reach single charge occupation.If setting the target voltage does not yield the targeted electron occupation in Qi ) the sequence is repeated with an increased (decreased) stress voltage to shift the voltage range further upward (downward).If a single electron is loaded at the target voltage configuration we stop applying stress voltages to Pi and analogously tune the potential of the other quantum dot.After the initial tune up (Fig. 1), we first follow the stressing procedure to lower the required plunger gate voltage ranges [V − Pi , V + Pi ] to reach single-electron occupancy at 1 V.During this process we adjust the barrier gate B2 voltage in order to maintain a significant tunnel rate.Then, we perform the stressing experiment and advance from point A to E in Fig. 2.b.Here, we only change the sensor gate S1 voltage and keep all other gate voltages constant (see supplementary section S8 for the voltage settings).Fig. 2.f shows charge stability diagrams recorded after tuning toward the predefined targets V T .A clear shift of the (1,1) charge region to higher plunger gate voltages and then back down is observable.Furthermore, after the completion of each tuning, setting the plunger gate voltages (V P3 , V P4 ) to V T = (V T , V T ) (white square marker) loads a single electron per quantum dot as also high- stressed gate: ) charge region V (1,1) in the (V P3 ,V P4 ) plane during the tuning procedure as defined prior to conducting the experiment.The color of the path refers to the plunger gate being stressed.(c) Actual trajectory of V (1,1)  followed during the tuning procedure.
. This demonstrates tunability of the chemical potentials and control over the electron occupation in a double quantum dot through the temporary application of stress voltage.Note that charge latching is reduced (increased) when tuning the voltage ranges [V − Pi , V + Pi ] upwards (downwards).This suggests a crosstalk effect of the applied stress voltages on the surrounding tunnel barrier potentials.Fig. 2.c shows the reconstructed evolution of the center point of the (1,1) charge region V (1,1) P4 ) during the tuning procedure (see methods section).Overall, the experimental trajectory reproduces qualitatively the intended one shown in Fig. 2.b.The pre-dominantly horizontal and vertical progressions in the (V P4 ) plane suggest limited crosstalk, i.e. applying stress voltages to one gate Pi only has a small effect on the charge transition voltages of the quantum dot below the other plunger gate.Quantitatively, we find slopes dV (1,1) Pi

/dV
(1,1) Pj between −0.31 V/V and −0.04 V/V.The sign of these slopes is consistent with the sign of the capacitive shift of the transition line voltage of Qj when the plunger gate voltage V Pi is changed (see supplementary section S1).Correcting for this effect, we obtain the change of the charge transition voltages of Qj induced exclusively by the application of stress voltages set to Pi.We find crosstalks of (+0.37 ± 0.03) V/V and (+0.19 ± 0.03) V/V for P3 on Q4 and P4 on Q3 respectively.Overall, while these crosstalk effects could be compensated for, the simple approach presented here allowed to tune the potentials of the quantum dots to the predetermined targets.

.d the center voltages V
(1,1) 3 and V (1,1) 4 are plotted as a function of the applied stress voltage V stress .We recover the typical hysteresis cycle observed when tuning pinch-off voltages using an analogous method in similar devices [38].Noticeably, for steadily decreasing stress voltages there is an initial increase in V (1,1) Pi before it rapidly drops to lower voltages at V stress ≈ −4 V.In Fig. 2.c this manifests as non-monotonic progressions of V (1,1) between the target points C and D. V initially increase by 40 mV and 180 mV, respectively, before they decrease and approach V T = 1.1 V. Summarizing, Fig. 2 demonstrates that the background potential in the quantum well can be reshaped such that each quantum dot can be occupied with one electron using uniform plunger gate voltages.

Time stability
To understand the impact of stress voltages on device stability, we record multiple charge stability diagrams as a function of time after the initial stress tuning towards V T = 1 V (A in Fig. 2.d).Fig. 3.a shows the extracted evolution of the plunger gate voltage range that keeps the quantum dots Q3 and Q4 in the single-electron occupation.Here, the time t refers to the time since the last application of a stress voltage and voltages are plotted relative to V T .We find that the double quantum dot system remains in the (1, 1) charge state for more than 15 h showing only a weak drift.This is confirmed by standard deviations of 3 mV, 3 mV, 2 mV, and 1 mV for V − P3 , V + P3 , V − P4 , and V + P4 , respectively, which remain negligible compared to the charging voltages of 148 mV and 87 mV for Q3 and Q4, respectively.Overlaying the charge stability diagrams recorded at t = 0 h and at t = 17 h, as depicted in Fig. 3.b, provides further confirmation of the device stability.Additional time traces demonstrating stability up to 40 h after the application of the last stress voltages are presented in supplementary section S2.Moreover, we find no increase in the charge noise sensed by the right SET when comparing to typical values for such devices (see supplementary section S3).Note that the charge noise amplitude measured by the SET might differ from the charge noise level that would affect the coherence of qubits in the array.Nevertheless, we conclude that there are no signs of decreased device stability caused by the application of stress voltages.0.9 1.0 1.1

Predetermined plunger gate voltage for tunnel coupled quantum dots
We now address the question whether single-electron occupation can still be achieved by a predetermined gate voltage, when changing the coupling between the quantum dots.In our double quantum dot system, we can control the interdot coupling by adjusting the barrier gate B34 voltage to tune the system from strong to weak coupling quantum dots.We achieve this by varying the barrier gate voltages between 0 V and −0.5 V.After setting a barrier gate voltage, we apply stress voltages to the plunger gates to obtain the (1, 1) charge state at V T = (1 V, 1 V).Fig. 4.a-e shows the resulting charge stability diagrams.The charge transition line pattern changes from exhibiting nearly diagonal lines at V B34 = 0 mV towards a rectangular grid-like pattern at V B34 = −500 mV, revealing the transition from high to low coupling.In all cases the application of stress volt- age sequences allows to obtain the (1, 1) charge state at V T = (1 V, 1 V).This is confirmed by the extracted voltage ranges [V − Pi , V + Pi ] plotted in Fig. 4.f.Crucially, this is achieved without defining virtual gates.We conclude that for a wide range of interdot couplings singleelectron occupation can be achieved at predetermined plunger gate voltage independently of the applied barrier voltage.
(1,1,1,1) charge state at (1,1,1,1) V Finally, we utilize our findings to tune a 2 × 2 quantum dot array such that the (N 1 , N 2 , N 3 , N 4 ) = (1, 1, 1, 1) charge state is the ground state when all plunger gate voltages are set to 1 V. Starting from the Q3-Q4 double quantum dot, we form the quantum dots Q1 and Q2 which are predominantly controlled by the plunger gates P1 and P2.Then, the system is tuned solely through tailored stress voltage sequences applied to the plunger gates.Fig. 5 shows two charge stability diagrams recorded after this tuning process unveiling four sets of charge transition lines.These can be associated with the four quantum dots by analysing further charge stability diagrams recorded by sweeping additional plunger gate combinations (see supplementary section S4).Yellow, orange, red and purple dashed lines mark the first two charge addition voltages of quantum dot Q1, Q2, Q3 and Q4, respectively.The target voltage configuration ) is shown by a white square marker and the voltage ranges that keep the system in the (1,1,1,1) charge state are indicated by horizontal and vertical bars.V T clearly falls between the first two charge transition lines for all four quantum dots confirming that we reached the targeted configuration.Note that all quantum dots are strongly affected by plunger gate P2 and P4 as observable in Fig. 5.b.However, in Fig. 5.a the voltages on P1 and P3 only seem to affect the charge occupation of Q1 and Q3.We speculate this behavior to originate from asymmetries in the gate layout and device imperfections [40].Crucially, we find that the stressing procedure is effective for the tuning of a nonlinear quadruple quantum dot array.

DISCUSSION
In summary, we have shown that single-electron occupation in quantum dots can be achieved at equal predetermined plunger gate voltage, by making use of a stressvoltage based procedure.Importantly, we find that after such a tuning the systems remains stable for hours only exhibiting small progressive drifts which do not affect the charge configuration.We envision that the stressing methodology may find several applications in semiconductor quantum technology.For instance, it may facilitate the operation of crossbar arrays which crucially rely on shared gate voltages [14,44].While our experiments suggest tunability of the entire potential landscape, more research is needed to understand the level of control over the barrier potentials.A predetermined gate voltage to set a given charge state can also relax the requirements on control electronics and facilitate their integration.Furthermore, we envision that stressing voltages can provide tunability of other parameters.For example, the g-tensor of germanium qubits is strongly dependent on the electric field [28,45], such that stressing voltages may provide tunability over the qubit resonance frequency.We therefore envision that stressing procedures may become a standard and essential routine in the tuning of large quantum circuits.

Heterostructure and device fabrication
The device under study in this work is fabricated on a 28 Si/SiGe heterostructure [39] which is based on a Si wafer.First, a linearly graded Si 1−x Ge x buffer with x varying from 0 to 0.3 is grown followed by a 300 nm relaxed Si 0.7 Ge 0.3 layer.A 7 nm purified (800 ppm) 28 Si layer defines the quantum well and is separated from the gate stack by another 30 nm thick relaxed Si 0.7 Ge 0.3 buffer that is passivated in dichlorosilane at 500 • C. Phosphorus ion implantation is utilized to contact the two dimensional electron gas and a 10 nm aluminum oxide layer precedes the deposition of gate electrodes.The latter are spread across three layers and made of Ti/Pd deposited via electron beam evaporation.They are separated by 5 nm thick layers of aluminium oxide.In all cases aluminium oxide is deposited via atomic layer deposition [28].

Setup and voltage pulses
All measurements are performed in a dilution refrigerator at a base temperature of ≈ 20 mK.The gate voltages are supplied by digital analog converters (DACs) with a resolution of 18 bit and a voltage range of ±4 V which was amplified to ±20 V for the plunger gates.The current through the SET is measured via a current-to-voltage converter connected to a digitizer module.Confinement and stress voltages are applied via the DACs while charge stability diagrams are recorded by sending fast voltage pulses.The latter are generated by an arbitrary waveform generator (AWG).DAC and AWG voltage signals are merged with a bias tee located on the sample PCB at the mixing chamber stage.AWG pulses are modified to correct for voltage drifts caused by (dis)charging of the bias tees.Furthermore, cross-capacitive shifts from P3 and P4 on the sensing dot potential are compensated for by proportionally adjusting V S1 when sweeping the plunger gate voltages V Pi (∆V S1 /∆V Pi < 0.01).

Local contrast normalization
In voltage scans spanning a large range, crosscapacitive coupling of the plunger gates to the SET can cause significant variations in sensor sensitivity.This leads to contrast fluctuations across the charge stability diagram and hampers identification of charge transition lines.We compensated for this effect by applying a local contrast normalization (LCN).In essence, a smoothed charge stability map is subtracted to compensate for a slowly varying offset after which a smoothed local variance is utilized to locally normalize the signal: Here, the asterisk denominates a convolution, I is the sensor signal and f Gaussian refers to a normal distribution with a mean and variance chosen between 4 and 50 pixels.

Extraction of characteristic voltages from charge stability diagrams
For each charge stability diagram we identify the coordinates of the charge triple degeneracy points (triple points) that constitute the corners of the (1,1) charge region.From these we calculate the voltage ranges [V − Pi , V + Pi ] that keep the system in the (1,1) charge state around the center point V (1,1) (in Fig. 1) or the target voltages V T (in all other figures).The center point V (1,1) of the (1,1) charge region is determined as the centroid of the triple points at the (2, 0) − (1, 1) and (1, 1) − (2, 0) charge transitions.Note that the voltage ranges [V − Pi , V + Pi ] are a measure of the maximum voltage variation on a single plunger gate for which the charge state remains constant.When taking into account more than a single gate voltage a polytope describes the applicable gate voltages that keep the charge state at single electron occupation.For instance, when considering two plunger gates the polytope would be the hexagon typically found in a double quantum dot honeycomb pattern.

While we utilize one-dimensional voltage ranges [V −
Pi , V + Pi ] to ease visualizations, after all stressing experiments the target voltage point V T lies inside the single charge occupation region (inside the respective gate voltage polytope).
We have used the triple points for the analysis because of their robustness against latching effects.For instance, in Fig. 1.b the dashed lines show reconstructed charge transition lines of quantum dot Q3 which has a weak coupling to the nearby charge reservoir.Consequentially, [V − Pi , V + Pi ] can include regions of meta-stable charge state (in between the observed and the reconstructed charge transition).This does not impact our conclusions because, at the end of all stressing experiments, the target voltage point V T lies in a region of stable charge state.
. Stress voltage induced crosstalk on quantum dots.(a) Trajectory of the (1,1) charge state center point V (1,1) in the (V P3 , V P4 ) plane during the tuning experiment shown in Fig. 2 of the main text (identical to Fig.A stress voltage applied to a plunger gate Pj not only alters the potential of the quantum dot Qj located directly underneath it but also affects neighbouring quantum dots Qi.We investigate this crosstalk by further analyzing the tuning of the Q3-Q4 double quantum dot presented in Fig. 2 of the main text.Fig. S1.a shows the trajectory of the center V (1,1) of the (1,1) charge state region in the (V P3 , V P4 ) plane (same as Fig. 2.c of the main text).The crosstalk manifests as a deviation from perfectly horizontal or vertical progressions of V (1,1) .We quantify it by applying a linear regression as exemplary shown in Fig. S1.b for the section from A to AB.The extracted slope s γ 34 is a measure for the crosstalk of plunger gate P4 onto quantum dot Q3.
Two mechanisms can explain the observed crosstalk as illustrated in Fig. S1.c: (1) Tuning the potential landscape of Q4 through the application of stress voltages also affects the potential of Q3 even if all gate voltages are reset to their initial value afterwards.For instance, this effect could be caused by the (de)charging of traps at the interface that capacitively couple to Q3 (C τ 34 ) [35-37, 47, 48].( 2) is defined as the middle point between the (1,0)-(1,1) and (1,1)-(1,2) charge transition at V P4 = V (1,1) P4 (and vice versa).Due to the capacitive coupling of P4 onto Q3 (C α 34 ) a shift in V (1,1) P4 is therefore also reflected in V (center point of the light and dark pink vertical bar).
To quantify the latter effect we determine the slope s α 34 of the Q3 charge transition lines at the (1,1) charge region.Fig. S1.e depicts an exemplary charge stability diagram during the tuning process with the respective Q3 charge transition lines indicated by dashed lines.All extracted s α 34 between the points A and AB in Fig. S1.a are plotted in Fig. S1.f.We find that s α 34 remains constant throughout the entire stress voltage sequence from A to AB.The same analysis steps are repeated for all sub parts between A and D of the trajectory in Fig. S1.a.Fig. S1.g summarizes all s γ ij (diamonds) and s α ij (downward pointing triangles).The magnitude of the cross-capacitance effect s α ij is consistently larger than the magnitude of the measured crosstalk s γ ij .To estimate the stress voltage crosstalk s τ ij solely caused by shifts of the intrinsic potential we subtract s α ij from s γ ij and plot the difference in Fig. S1.h.We find a positive voltage stress related crosstalk, which has a similar magnitude as the capacitive effect s α ij .As s τ ij and s α ij have a different sign they partially cancel each other and lead to a reduced effective crosstalk s γ ij when applying stress voltage sequences.Fig. S2 shows two additional time traces not shown in Fig. 3 in the main text.Note that in Fig. S2.b and c the recording of the time traces was started 20 h and 4 h after the application of the last stress voltage, respectively.The additional curves confirm that after the application of a stress voltage tuning the system remains in a (1,1) charge state for 40 h at least only exhibiting small progressive drifts.

S3. CHARGE NOISE AFTER APPLYING STRESS VOLTAGES
As the presented tuning procedure might alter the configuration of charge traps in the heterostructure (see supplementary section S5) we investigate the system charge noise after applying stress voltages.Specifically, we measure time traces of the current through the sensing quantum dot (underneath S1) and compute the power spectral density (PSD).To obtain maximum sensitivity of the sensor current to potential fluctuations we tune the sensor plunger gate voltage V S1 to the flank of a Coulomb peak.Fig. S3.a, b and c depict PSD spectra obtained after tuning to the target point A, C and E in Fig. 2.b, respectively.Note that target points A and C are reached by applying positively signed stress voltages and target point E is reached by applying negatively signed stress voltages.The charge noise curves follow the typical 1/f frequency dependence.Therefore we fit them between 0.1 Hz and 5 Hz with S fit ϵ = A × f −κ (black line).We find noise amplitudes of √ A = 0.71 µeV/Hz 1/2 , √ A = 0.60 µeV/Hz 1/2 and √ A = 0.78 µeV/Hz 1/2 as well as exponents κ = 0.96.κ = 1.38 and κ = 1.07 for target point A, C and E, respectively.These values are comparable to charge noise amplitudes in Si/SiGe reported in the literature [49][50][51] and charge noise values measured in the same device during an earlier cooldown [39].Thus, we find no indication that a spin qubit implemented in a stressed quantum dot would be impaired by a degraded noise environment.However, further research is required as the charge noise sensed by the sensor might not be representative for the charge noise affecting qubits that are tuned in the quantum dots.

S4. IDENTIFICATION OF THE FOUR QUANTUM DOTS
In order to identify the quantum dots visible in Fig. 5 of the main text we measure multiple charge stability diagrams by sweeping all pairwise combinations of the device plunger gate voltages.The obtained charge stability diagrams are plotted in Fig. S4.The center left and bottom center panel are identical with the charge stability diagrams shown in Fig. 5 of the main text.All maps are obtained at the same gate voltage configuration and at their center point all plunger gates are set to 1 V.
The charge stability diagrams can be analyzed starting from one charge transition line, e.g. the first vertical charge transition line in the center left panel (indicated by a yellow dashed line).Due to its strong coupling to plunger gate P1 we identify it as a charge transition line of quantum dot Q1.We mark the crossing point of this Q1 charge transition line with the V P1 = 1 V line (vertical white line) by a yellow circle.Then we place another yellow circle marker at identical V P3 on the V P2 = 1 V line in the center panel of the figure.The vertical white lines inside one row of figure panels are identical line cuts in the gate voltage space.Therefore both marked points identify the same charge transition line of the same quantum dot (Q1).Analogously two charge stability diagrams in one column of figure panels can be compared.By repeating the process for all neighbouring charge stability diagrams one can identify the charge transition lines of four quantum dots Q1-Q4.Note that the charge transition lines of quantum dot Q4 (purple) latch when the sweep direction (black arrow in the upper right of each panel) is nearly perpendicular to the charge transition lines.Therefore the crossing point of the first Q4 charge transition line with the V P1 = 1 V line in the bottom left panel and the crossing point with the V P3 = 1 V line in the bottom right panel differ from the crossing point with the V P2 = 1 V line in the bottom center panel.Furthermore, in the left column another nearly vertical charge transition line is visible in the background.However, it shows negligible coupling to the other charge transition lines and likely is a signature of a spurious defect quantum dot outside but close to the active device region.

S5. UNDERLYING PHYSICAL MECHANISMS
Applying a stress voltage to a selected gate electrode possibly alters the occupation of charge traps in the gate dielectrics and heterostructure directly underneath [35-37, 47, 48].As the electric field bends the conduction band electrons might tunnel into or out of these charge traps.Removing the stress voltage then effectively freezes their occupation which permanently alters the intrinsic potential landscape.Charge traps can be present in the oxide layer [52][53][54][55], originate from unpassivated silicon and germanium dangling bonds [53][54][55] or arise from mechanical stress induced by the deposition of metallic gate electrodes [30,32].Furthermore, also the relocation of mobile ions might change the intrinsic potential [56].Note that these processes in general are independent of the quantum well material itself and stress-voltage-controlled shifts of the intrinsic potential also have been observed in Ge/SiGe heterosturctures [38,57].

Figure 1 .
Figure 1.Device and tuning of a double quantum dot.(a) Scanning electron micrograph of a device nominally identical to the one under study.Confinement (Ci) and barrier (Bi and Bij) gates are designed to define four quantum dots indicated by the white circles.Their charge occupation is controlled by four plunger (Pi) gates.Confinement gates are outlined by dashed lines for clarity.A sensor quantum dot is formed under S1 and measured in transport.(b) Charge stability diagram showing the single-electron occupation of the Q3-Q4 double quantum dot formed underneath P3 and P4.The plotted signal is locally contrast normalized (LCN) to increase the visibility of the charge transition lines as described in the methods section.Dashed lines connect charge triple degeneracy points and thereby indicate transitions of the charge ground state which cannot be observed directly due to latching effects.The plunger gate voltage ranges [V − Pi , V + Pi ] that set a (1, 1) charge state are indicated by vertical and horizontal bars.The ranges are extracted around the center point of the (1,1) charge region (see methods).Unprocessed data shown in supplementary section S6.(c) Plunger gate voltage ranges [V − Pi , V + Pi ] as extracted in (b).

Fig. 1 .
b depicts a charge stability diagram recorded after the initial tuning.It shows the typical honeycomb pattern of a double quantum dot and depletion down to the (N 3 , N 4 ) = (1, 1) charge state with N i the charge occupation of Qi.The charge stability diagram reveals a large asymmetry in the plunger gate voltages required to reach the single-electron regime.The voltage ranges [V −

Figure 2 .
Figure 2. Single-electron occupation at predetermined plunger gate voltages through voltage stressing.(a) Schematic of the stress-measure sequence applied to shift the voltages required to obtain the (1, 1) charge state.Increasing stress voltages Vstress are applied for tstress = 1 min interleaved by charge stability diagram measurements.(b) Expected trajectory for the center of the (1,1) charge region V(1,1) in the (V P3 ,V P4 ) plane during the tuning procedure as defined prior to conducting the experiment.The color of the path refers to the plunger gate being stressed.(c) Actual trajectory of V(1,1)  followed during the tuning procedure.The triangle, circles and diamond mark the starting point, (intermediate) targets and the endpoint of the path, respectively.Black arrows indicate the time flow.(d) V Figure 2. Single-electron occupation at predetermined plunger gate voltages through voltage stressing.(a) Schematic of the stress-measure sequence applied to shift the voltages required to obtain the (1, 1) charge state.Increasing stress voltages Vstress are applied for tstress = 1 min interleaved by charge stability diagram measurements.(b) Expected trajectory for the center of the (1,1) charge region V(1,1) in the (V P3 ,V P4 ) plane during the tuning procedure as defined prior to conducting the experiment.The color of the path refers to the plunger gate being stressed.(c) Actual trajectory of V(1,1)  followed during the tuning procedure.The triangle, circles and diamond mark the starting point, (intermediate) targets and the endpoint of the path, respectively.Black arrows indicate the time flow.(d) V (1,1) P3 (bottom) and V (1,1) P4 (top) as a function of the applied stress voltage Vstress.The triangle, circles and diamond mark the same points as in (c) and black arrows indicate the time flow.(e) Plunger gate voltage ranges [V − Pi , V + Pi ] that keep the double quantum dot in the (1, 1) charge state after tuning (see methods).Targets are indicated by the dotted lines.(f) Corresponding charge stability diagrams recorded after the application of the respective stress voltage sequences.The white square markers show the target voltages V T = (V T , V T ).Plunger gate voltage ranges [V − Pi , V + Pi ] that keep the system in the (1, 1) charge state are indicated by vertical and horizontal bars.Dashed lines indicate transitions of the charge ground state which cannot be observed directly due to latching effects.Unprocessed data shown in supplementary section S6.

Figure 3 .
Figure 3. Stability of the (1,1) charge state after stress tuning.(a) Time traces of the plunger gate voltage ranges that keep the system in the (1, 1) charge state (see methods for the definition) after the application of a sequence of increasing stress voltages.t is the time after the application of the last stress voltage.Note that the underlying charge stability diagram measurements were interleaved with charge noise measurements on the sensor (see supplementary section S3).Additional traces are presented in supplementary section S2.(b) Overlay of charge stability diagrams taken at the beginning (star, olive green) and end (hexagon, light green) of the time trace shown in (a).Horizontal and vertical bars indicate the respective plunger gate voltage ranges that keep the system in the (1,1) charge state.Dashed lines indicate transitions of the charge ground state which cannot be observed directly due to latching effects.Unprocessed data shown in supplementary section S6.

Figure 4 .
Figure 4. Single-electron occupation at predetermined plunger gate voltage for high and low interdot coupling.(a)-(e) Charge stability diagrams measured after tuning the system through applying stress voltages such that the (1,1) charge state is the ground state when applying the plunger gate voltages V T = (1 V, 1 V) (white square marker).In each case a different barrier gate voltage V B34 is set before the tuning (labelled in the plot titles).The range of plunger gate voltages [V − Pi , V + Pi ] that keep the system in the (1, 1) charge state is indicated by horizontal and vertical bars (see methods).Dashed lines indicate transitions of the charge ground state which cannot be observed directly due to latching effects.The unprocessed data is shown in supplementary section S6.(f) Plunger gate voltage ranges [V − Pi , V + Pi ] extracted from (a)-(e).The dotted line indicates the target voltage V T = 1 V.

Figure 5 . ( 1 , 1 , 1 , 1 )
Figure 5. (1,1,1,1) charge state at 1 V on all plunger gates (a), (b) Charge stability diagrams recorded after applying stress voltage sequences to tune the (1,1,1,1) charge state to be the ground state when all plunger gate voltages are set to 1 V.The first two transition lines of each quantum dot are indicated by dashed lines.The voltage ranges to keep the system in the (1,1,1,1) charge state are indicated by horizontal and vertical bars (see methods).A white square marks the point when all plunger gates are at 1 V.The plotted signal is the summation of several charge stability diagrams with identical voltage ranges recorded for slightly varied voltages on the SET plunger S1 (see supplementary section S7).Contrast is enhanced by a local contrast normalization (LCN).(a) shows charge transitions of Q1 and Q3 and (b) exhibits charge transition lines of all four dots.
Figure S1.Stress voltage induced crosstalk on quantum dots.(a) Trajectory of the (1,1) charge state center point V(1,1) in the (V P3 , V P4 ) plane during the tuning experiment shown in Fig.2of the main text (identical to Fig. 2.c).(b) Part of the trajectory between the points A and AB.The black line is a linear fit to the data to determine the slope s γ 34 that quantifies the crosstalk of plunger gate P4 on quantum dot Q3.(c) Illustration of a device cross section portraying the capacitive effect of the plunger gate voltage V P4 on the potential of quantum dot Q3 (C α 34 ) and the crosstalk effect of applying stress voltages to plunger gate P4 on the potential of quantum dot Q3 (C τ 34 ).(d) Schematic charge stability diagram illustrating how the charge transition voltages of quantum dot Q3 shift when changing the voltage on plunger gate P4.Grey lines indicate the charge transition lines before and black lines after changing the potential of Q4 through applying stress voltages.For illustration purposes the interdot coupling between Q3 and Q4 and the capacitive coupling of P3 onto Q4 are neglected.(e) Example charge stability diagram taken at point A in (a).The slope s α 34 of the transition lines of Q3 (black dashed lines) are determined as a measure for the relative capacitive effect of plunger gate P4 onto the potential of quantum dot Q3.To ensure robustness against distortions from charge latching effects, the Q3 charge transition lines are defined as the lines connecting the respective triple charge degeneracy points.(f) All extracted s α 34 during the tuning from point A to AB in (a).(g) Crosstalk s γ ij caused by stressing plunger gate Pi (diamonds) and cross-capacitance effect s α ij of plunger gate voltage V Pj (downward pointing triangles) onto the potential of quantum dot Qi along the trajectory in (a).Between C and CD and CD and D only the last ten points are fitted to extract s γ ij .Due to a limited number of data points no values are shown for the tuning between D and E. (h) Stress voltage induced crosstalk effect s τ ij of plunger gate Pj onto the potential of quantum dot Qi corrected for the capacitive coupling of plunger gate Pj onto the potential of quantum dot Qi.

(1, 1 )
P3 .Fig.S1.d portrays the mechanism.It shows a schematic charge stability diagram before (grey charge transition lines) and after (black charge transition lines) tuning the potential below P4 through the application of stress voltages.As the Q3 charge transition lines are tilted by the cross-capacitance C α 34 , a change in V

Figure S2 .
Figure S2.Additional time traces after applying stress voltage sequences.(a)-(c) Time traces of the voltage ranges [V − Pi , V + Pi ] after the application of a stress voltage sequence.(a), (b) and (c) are recorded after tuning to the target points A, C and E as presented in Fig. 2 in the main text, respectively.t is the time after the application of the last stress voltage.(a) is identical to Fig. 3.a in main text.Note that the underlying charge stability diagram measurements were interleaved with charge noise measurements on the sensor (see supplementary section S3).

2 Figure S3 .
Figure S3.Sensor charge noise after applying stress voltages.(a) Power spectral density (PSD) extracted from sensor current time traces recorded after tuning to point A in Fig. 2.b of the main text.Sϵ = α 2 SI /|dI/dV S1 | with α the lever arm of sensor plunger gate S1 extracted from coulomb diamonds, |dI/dV S1 | the maximum slope of the coulomb peak and SI the PSD of the current through the sensor [49].For the measurement the sensor plunger voltage V S1 is tuned to the Coulomb peak flank, the voltage for which the sensing quantum dot is most sensitive to potential fluctuations.The black line is a fit to Sϵ between 0.1 Hz and 5 Hz with S fit ϵ = A × f −κ .The noise amplitude A at 1 Hz is given in the upper right.κ = 0.96 (b) and (c) Same as (a) but recorded after reaching target point C and E in Fig. 2.b of the main text, respectively.κ = 1.38 for C and κ = 1.07 for E.

Figure S4 .
Figure S4.Charge stability diagrams identifying the quantum dots Q1-Q4.Charge stability diagrams recorded for all plunger gate combinations.The arrow in the upper left corner indicates the sweep direction.The center point (crossing point of the white lines) for each charge stability diagram corresponds to the same voltage configuration with V P1 = V P2 = V P3 = V P4 = 1 V. Horizontal white lines mark identical line cuts in the gate voltage space inside each column of charge stability diagrams.Vertical white lines mark identical line cuts in the gate voltage space inside each row of charge stability diagrams.Colored dashed lines indicate charge transitions and colored circles mark crossing points of the charge transitions with the white lines.Each color refers to a quantum dot as indicated by the legend in the upper right.To enhance the visibility of the charge transition lines the derivative of the sensor current was taken ad a local contrast normalization (LCN) was applied.