Field and Thermal Emission Limited Charge Injection in Au–C60–Graphene van der Waals Vertical Heterostructures for Organic Electronics

Among the family of 2D materials, graphene is the ideal candidate as top or interlayer electrode for hybrid van der Waals heterostructures made of organic thin films and 2D materials due to its high conductivity and mobility and its inherent ability of forming neat interfaces without diffusing in the adjacent organic layer. Understanding the charge injection mechanism at graphene/organic semiconductor interfaces is therefore crucial to develop organic electronic devices. In particular, Gr/C60 interfaces are promising building blocks for future n-type vertical organic transistors exploiting graphene as tunneling base electrode in a two back-to-back Gr/C60 Schottky diode configuration. This work delves into the charge transport mechanism across Au/C60/Gr vertical heterostructures fabricated on Si/SiO2 using a combination of techniques commonly used in the semiconductor industry, where a resist-free CVD graphene layer functions as a top electrode. Temperature-dependent electrical measurements show that the transport mechanism is injection limited and occurs via Fowler–Nordheim tunneling at low temperature, while it is dominated by a nonideal thermionic emission at room and high temperatures, with energy barriers at room temperature of ca. 0.58 and 0.65 eV at the Gr/C60 and Au/C60 interfaces, respectively. Impedance spectroscopy confirms that the organic semiconductor is depleted, and the energy band diagram results in two electron blocking interfaces. The resulting rectifying nature of the Gr/C60 interface could be exploited in organic hot electron transistors and vertical organic permeable-base transistors.

S3 d) CVD graphene transfer CVD graphene foil (Cu/Gr/PMMA) is placed to float in a copper etchant (Transene CE-100) for 1h, the PMMA layer facing upwards. Once the copper is completely etched (Gr/PMMA), the etchant is removed and replaced with de-ionized water, twice. Then, the foil is transferred to a 10% HCL cleaning solution for 5 min and transferred back to de-ionized water, twice. The floating graphene foil (Gr/PMMA) is transferred onto the substrate (Si/SiO2/Au/C60/Gr/PMMA) and let dry in air for 1 h.

e) PMMA removal from graphene
The chip is annealed overnight at 80°C in vacuum (~1 mbar). The top PMMA layer is removed in Acetone (5 min) and the chip annealed again overnight at 80°C in vacuum (~1 mbar).

f) RIE patterning of the graphene top electrode
The chip is spin-coated with an AZ1505 optical resist (4000 rpm, 40 s) and backed at 110°C for 1 min. The device area is exposed for 1.8 s to UV light (lamp intensity 11 mW/cm2) through an optical mask. The exposed optical resist is developed in AZ400K (400K:DIW, 1:4) for 15 s and rinsed with de-ionized water. Then, RIE is used to remove the unprotected graphene (O2, 30 sccm, 25 W).

g) Optical resist removal from graphene
The optical resist protecting the graphene electrode is removed with Acetone (2 min), then the chip is rinsed in de-ionized water and blown dry with nitrogen. annealing measured under vacuum (~10 -6 mbar), at 50 K, and in dark. (d) I-V traces of the devices exposed to air. The graphene resistance for a representative device for each diameter, extracted from the linear fit of the I-V traces, is given in Table S1. Table S1. Graphene resistance (measured in Ω) of a representative Graphene Bridge device for each size measured under different environment conditions. Similar resistances are measured for graphene at room temperature (293K) in dark, and after annealing (110°C for 12h) in dark. Lower resistance is found at low temperature (50K), possibly due to higher charge mobility, and in air conditions (293K in dark), as expected from an increased charge carrier density due to the O2 and H20 p-doping of graphene. Under all conditions, the resistance of the Graphene Bridge is lower than the one of the Vertical Stack. Therefore, the series resistance Rs shown in the circuit of Figure   4 can be neglected, and the current across the Vertical Stack is limited by the interfaces.

Induced charge carrier density in graphene due to C60
The induced charge carrier density in graphene is deduced from a parallel plate capacitor model, Eq. S1 Where = 0 ⁄ is the capacitance per unit area, t is the thickness of the oxide (300 nm) and is the dielectric constant of SiO2 (ca. 3.9). Since the charge neutrality point is shifted by roughly 20 V, as shown in Fig. S3, the induced charge density of graphene doped by C60 is ca. ≈   Table S2 shows the ideality factors and energy barriers of SB1 and SB2 obtained from the Richardson plots ( Fig. S6 and Fig. S7) and considering the non-ideal Schottky diode model with ideality factor n. The resulting effective Richardson constant A ** is voltage dependent and vary in the range 10 1 − 10 3 −2 −1 for |V| > 5 V. The energy barrier and ideality factor of SB1 are smaller than SB2 (i.e. Φ 01 < Φ 2 and n 1 < n 2 ), following the same trend observed for the results of the DSB model. The higher ideality factors n 1,2 obtained from the individual Schottky diode model is possibly due to the presence of the second energy barrier and/or to the voltage dependent Richardson constants. This could also lead to a slight overestimation of the energy barriers Φ 01,2 .

Discussion on the non-ideal Schottky diode model fitting of individual interfaces (SB1 and SB2)
For this reason, in the DSB model presented in Figure 2, the Richardson constant was set to the fixed value of * * = 100 −2 −1 (red dashed line in Fig. S6 and Fig. S7), and the energy barriers error induced by the Richardson constant, varying in the range 10 1 − 10 3 −2 −1 (observed range for the individual Schottky diode model, Fig. S6 and Fig. S7), is below 0.1eV, as shown in Figure S8.