Versatile Nanoscale Three-Terminal Memristive Switch Enabled by Gating

A three-terminal memristor with an ultrasmall footprint of only 0.07 μm2 and critical dimensions of 70 nm × 10 nm × 6 nm is introduced. The device’s feature is the presence of a gate contact, which enables two operation modes: either tuning the set voltage or directly inducing a resistance change. In I–V mode, we demonstrate that by changing the gate voltages between ±1 V one can shift the set voltage by 69%. In pulsing mode, we show that resistance change can be triggered by a gate pulse. Furthermore, we tested the device endurance under a 1 kHz operation. In an experiment with 2.6 million voltage pulses, we found two distinct resistance states. The device response to a pseudorandom bit sequence displays an open eye diagram and a success ratio of 97%. Our results suggest that this device concept is a promising candidate for a variety of applications ranging from Internet-of-Things to neuromorphic computing.


Structural Images
Process control chips were fabricated in parallel with the devices presented in the manuscript.They have the same layers and thicknesses as the main chip (from bottom to top: Si / 200 nm SiO 2 / 3 nm Ti / 47 nm Pt / 4 nm SiN / 2 nm TiN / 1 nm Cr / 24 nm Ag / 17 nm Pt / 3 nm Cr).They served to validate the processes such as the physical etching step without the risk of damaging the main chip.A cross section of such a process control chip is shown in Figure S1 and shows the layer stack of 50 nm bottom electrode (BE, Ti/Pt), 6 nm nitrides, 44 nm top electrode (TE, Cr/Ag/Pt/Cr).On top, the remains of the resist, hydrogen silsesquioxane (HSQ), can be seen.The thicknesses were extracted from the SEM image using ImageJ.On the main chip, test structures were fabricated for non-invasive checks during the fabrication process.In Figure S2, such a test structure to measure the width of the bottom electrode and verify the contact pad resistance is shown.The planned width was 70 nm.The measurements were done with the SEM directly and show the actual fabricated devices to be slightly narrower.

Two-Terminal Set Time
We evaluate the set time of the two-terminal section of our devices by adding a series resistance  set 10 kΩ and applying input voltage pulses of 4 V. Two read pulses of 0.25 V were used to measure the device state before and after the set pulse.An exemplary measurement is shown in Figure S3.Using the definition laid out by Lübben et al. 1 , we evaluate as the time between the two rising edges at 50% height.Evaluating  set for 3 devices, we find a mean value of . set 1.0 μs

Retention
Pulsed retention measurements were carried out using the same bias voltage and series  B = 1.5 V resistance as in the pulsed measurements shown in Figure 4.A transimpedance amplifier (TIA)  S = 1 MΩ was used to amplify the current and translate it into a voltage.A read pulse of amplitude and 0.1 V 1 ms duration was followed by an intentionally long set pulse of duration to mimic longer operation as 125 ms used in the manuscript.We measured the state of the device using twenty read pulses ( ) with 0.1 V, 1 ms 1 of wait time in between.We find that the device turns off in less than In Figure S4

Full I-V Cyclic Voltammetry
The full data shown in Figure 1 and 2 of the manuscript is reproduced here.The current is plotted in logarithmic scale.All cycles are plotted in a light color, while the median cycle is highlighted in a bold color.
Certain cycles exhibit currents above 10 nA for negative source-drain voltages .However, this  SD observation alone does not imply nonvolatility, especially when considered alongside the short retention times depicted in Figure S4 of the Supporting Information "Retention" and the data presented in "Reset Voltage Analysis" in the Supporting Information.
The spread in the observed onset of the device is in the typical range for Ag-based systems.

Reset Voltage Analysis
The reset voltage was extracted from the measurements shown in Figure 2 S1.The low reset voltages fit well with the observed low retention.

Continuous Gate Change Measurements
Using the IV measurement setup used in Figures 1 and 2, we apply a triangular voltage signal on the gate ( ), while keeping the source-drain voltage constant and the drain grounded, as shown in  GD  SD Figure S7(a) in purple and blue respectively.We perform this sweep two times and find that the gate voltage can turn the device on and off in a controllable way.In Figure S7  .We observe that negative gate voltages can turn the device on. GD

Leakage Currents
Leakage currents between gate and source or drain electrodes have been measured.To this end, we applied the voltages as used in our experiments for , thereby gathering seven data points with an 2 s integration time of for both and .We repeated these measurements on three devices.The 40 ms  SG  DG mean current of all data points is shown in Table S2

Gate Influence on the Resistance State Retention
Gate influence on the resistance state's retention was investigated using the same setup as in Figure 4-6 of the manuscript.The bias voltage was held constant while a rectangular voltage signal was applied to  B the gate ( ).After several pulses, the gate was set to floating, leading to a disconnected , as  GD  GD illustrated in Figure S8(

Figure S1 :
Figure S1: Cross-sectional scanning electron microscopy (SEM) image of a control chip fabricated in parallel with the device chip.It shows the layers (BE/nitrides/TE) with their corresponding thicknesses (50 nm/6 nm/44 nm).A layer of resist (HSQ) is left on-top of the TE.One can see a steep etching of the layers.The thickness extractions were performed with ImageJ.

Figure S2 :
Figure S2: Top view of an SEM image showing the actual measured width of the 70 nm structured bottom Pt wires.

Figure S3 :
Figure S3: Pulsed set time measurements with a series resistance of 10 kΩ and an input voltage pulse amplitude of 4 V. (a) Readset-read operation.In blue, the incoming voltage pulse is shown.The read pulse has a height of 0.25 V, the set voltage pulse of 4 V.In green, the voltage between the series resistance and the device-under-testing is shown.During the first read pulse, the device is in off-state.During the application of the set pulse, the device turns on.Finally, the device is still in the on-state during the second read pulse.Between the flanks, only every 20 th data point is plotted for legibility.At the flanks, all data points are shown.(b) A closer look at the set operation.In this example, the set time was evaluated to be 1.08 .
Figure S4: Pulsed retention measurements using the same bias voltage and series resistance as in the pulsed   = 1.5    = 1  measurements shown in Figure 4 of the manuscript.(a) The bias voltage supplied by the AWG is shown.The read pulses have an amplitude of and duration of .After a first read pulse, a long set pulse and 20 read pulses with wait time 0.1  1  125  1  in between follow.(b) We amplify the current after the device with a TIA and measure the output voltage.(c) End of the set pulse and the twenty read pulses are shown in detail.The AWG voltage (blue) and the measured TIA voltage (green) show that the device turns off after about .37

2 - 4 Figure
Figure S5: Full IV sweeps of the measurements shown in Figure 1 and 2 of the main text.All cycles are shown in light color, while the median cycle is highlighted.(a) Two terminal IV sweeps with a floating gate.(b) Three terminal IV sweeps with gate voltage (-1 V, +1 V) shown in blue and orange, respectively.
and Figure S5(b).It was evaluated as the voltage, where the device resistance with being the mean of the  DUT > 10 on  on resistances at and the next 9 data points.A histogram of the found reset voltages is shown in  set  reset Figure S6 and the statistical data is presented in Table

Figure S6 :
Figure S6: Reset voltage evaluation of the gate biased measurements shown in Figure 2 and Figure S5(b).The reset voltage is extracted at the point where .  > 10  Applied Gate Voltage   = +     = -  Mean   0.1431 V 0.0755 V Median   0.1250 V 0.1250 V Standard Deviation   0.1250 V 0.0954 V (b), the current response of  SD the source-drain contact is plotted against time.A compliance current of was set.In  cc = 100 nA Figure S7(c), the same data is plotted against the gate voltage showing an onset for negative gate voltages.

Figure S7 :
Figure S7: Continuous gate voltage sweep with the SD voltage kept constant.(a) In purple, the triangular gate voltage signal is shown ( ).In blue, the constant source-drain voltage is shown ( ).(b) Overlay of the  GD ∈ [ -2.5 , + 2.5 ]  SD = 0.4  source-drain currents of two sweeps over time.One can observe a turn on in both cycles at around 70 s.(c) is plotted as a    SD function of.We observe that negative gate voltages can turn the device on. GD a), where the transition from solid to dashed purple line indicates this event.Throughout this process, remains unchanged and is shown in blue.The measured source-drain voltage  B , shown in Figure S8(b), was used to calculate the device resistance , depicted in Figure S8(c). SD  DUT We evaluate the retention time ( ) as the time between the end of the last gate pulse and the subsequent  drop of .The resistance drops by > 50 % in when no gate signal is applied, as shown in  DUT  = 100 μs Figure S8(d).To derive this, three resistance states are extracted from the data: the mean resistance  VG + when applying a positive gate bias, the resistance with floating gate, and the midpoint of these  float  half two values.The gated retention time is defined as the time difference between the last point with the  connected gate and the first point after the resistance has dropped below . half This time scale agrees with the RC-time of the used setup, as discussed in the Method Section.

Figure S8 :
Figure S8: Resistance state retention when the gate is set to floating.(a) The bias voltage , in blue, is held constant whereas the   gate voltage , in purple, is first pulsed and then disconnected.This is depicted by the transition from a solid to a dashed line.  (b) The source-drain voltage is measured and used to calculate the device's resistance state.(c) The calculated device   resistance .During the rectangular gate pulses, the device resistance switched between two states.Once the gate contact is   disconnected, the resistance relaxes to an intermediate state.(d) Zoom-in to the retention measurement.The time between the gate is disconnected and the resistance is falling below is extracted as the gated retention time . half  = 100 μs

Table S1 :
Statistical data evaluation of the presented reset voltages.

Table S2 :
below.Hence, leakage currents to the gate are significantly below source-drain current in compliance (). SG ,  DG ≪ 100 nA ≤  SD,cc Leakage current data.In the left column, the applied voltage between the corresponding contacts is shown.All currents are below or equal to 1.6 nA, which is considerably less than the source-drain currents in the gated measurements.