Flux-Tunable Josephson Diode Effect in a Hybrid Four-Terminal Josephson Junction

We investigate the direction-dependent switching current in a flux-tunable four-terminal Josephson junction defined in an InAs/Al two-dimensional heterostructure. The device exhibits the Josephson diode effect with switching currents that depend on the sign of the bias current. The superconducting diode efficiency, reaching a maximum of |η| ≈ 34%, is widely tunable—both in amplitude and sign—as a function of magnetic fluxes and gate voltages. Our observations are supported by a circuit model of three parallel Josephson junctions with nonsinusoidal current–phase relation. With respect to conventional Josephson interferometers, phase-tunable multiterminal Josephson junctions enable large diode efficiencies in structurally symmetric devices, where local magnetic fluxes generated on the chip break both time-reversal and spatial symmetries. Our work presents an approach for developing Josephson diodes with wide-range tunability that do not rely on exotic materials.

Nonreciprocal transport phenomena play a key role in modern electronics, with semiconductor diodes serving as the fundamental components for numerous devices [1].In analogy to the semiconductor diode, whose electrical resistance strongly depends on the current direction, a superconducting diode allows a larger supercurrent to flow in one direction compared to the other [2].Nonreciprocal supercurrents were recognized already in the 1970s in superconducting quantum interference devices (SQUIDs) based on superconducting bridges [3] and tunnel Josephson junctions (JJs) [4,5], arising as a consequence of the finite loop inductance.Direction-dependent switching currents were also observed in conventional superconducting thin films and interpreted as a manifestation of microscopic asymmetries in the device geometry [6].More recently, the superconducting diode effect (SDE) has sparked renewed interest, driven by its connection to fundamental properties of a diverse range of superconducting systems, where the breaking of both inversion and time-reversal symmetries is required for the effect to occur.Since its observation in artificial superlattices [7], the SDE has been the subject of thorough experimental and theoretical investigation, both in junction-free thin films [8][9][10][11][12][13] and JJs based on semiconductors with spin-orbit coupling [14][15][16][17], finite-momentum superconductors [18][19][20] or multilayered materials, realizing sizeable asymmetries even without external magnetic fields [21][22][23][24][25][26][27][28].
An alternative platform proposed to achieve the SDE in Josephson devices-where it is usually referred to as Josephson diode effect (JDE)-relies on a super-current interferometer, where two JJs with nonsinusoidal current-phase relations (CPRs) are combined in a SQUID [29,30].Such CPRs, containing contributions from higher harmonics than the conventional 2π-periodic component, are routinely attained in highquality superconductor-semiconductor planar materials [31][32][33][34], where hybrid JJs host Andreev bound states (ABSs) characterized by high transmission.Key ingredients for the JDE to occur in this system are the different harmonic content between the two JJs, and a magnetic flux threading the SQUID loop [29], as recently demonstrated in two-dimensional (2D) electron [35,36] and hole [37] systems, obtaining large diode efficiencies at equilibrium up to approximately 30%.Furthermore, threeterminal Josephson devices without phase control were shown to realize the JDE by exploiting high harmonic terms in the CPR [38], multiple bias currents [39,40] and Andreev molecules [41,42].
In this work, we report on the superconducting transport properties of a superconductor-semiconductor fourterminal JJ (4TJJ) embedded in a double-loop geometry.Supercurrents are tuned by magnetic fluxes threading the superconducting loops and by gate electrodes that control the number and transmissions of ABSs.We find strong JDE, tunable in both efficiency and sign with gate voltages and two independent superconducting phasescontrolled via integrated flux-bias lines, without the need for external magnetic fields-reaching a peak efficiency of ±34%.One of the loops was further controlled by gating an additional JJ with large critical current, enabling operation of the device in a single-loop configuration.We provide an in-depth explanation of the JDE in our system by means of a simple circuit model, which maps our device to the combination of two SQUIDs, or a bi-SQUID.Simulations are performed both in an idealized case with minimal assumptions, and in an extended version that accurately captures the experimental results.We demonstrate several novelties with respect to previous work.First, we devise a geometry that combines both gate control of the current path and phase tunability in a 2D space, offering new insights into multiterminal JJs.Second, the phase-tunable bi-SQUID allows for a large diode efficiency to occur without the need of a JJ imbalance in harmonic content, which is required in conventional interferometers [29].Third, phase control enables large tuning of the JDE in amplitude and sign, including a vanishing diode efficiency in extended regions of the phase space.In the light of our results, multiterminal JJs in superconductor-semiconductor hybrid systems offer advantages that are pivotal for the realization of nonreciprocal transport phenomena.Thanks to the nonsinusoidal CPR and the possibility to break time-reversal symmetry solely by flux biasing, large and tunable diode efficiencies are naturally obtained without the need of an external magnetic field.Future work might further expand the study of multiterminal devices to realize nonreciprocal transport in the linear regime [43,44], presenting opportunities for innovative applications.

Flux-tunable multiterminal Josephson junction
The device under study, consisting of a multiterminal JJ embedded in a double-loop geometry, is displayed in Fig. 1.It was realized in an InAs/Al heterostructure [45,46], where the epitaxial Al layer was selectively removed to expose the III-V semiconductor below.We defined four superconducting terminals, labeled S, L, M and R, coupled to a common semiconducting region.Lithographically, the minimum distances between neighboring terminals were 30 nm (for L-M and R-M) and 50 nm (for S-L and S-R), while opposite terminals had separations of 100 nm (L-R) and 120 nm (S-M).All junctions were short with respect to the superconducting coherence length in the InAs 2D electron gas, estimated to be approximately 600 nm (see Methods section).Terminals L, M and R were connected to a common node (D) forming two superconducting loops, which enabled independent control over two phase differences [47,48], ϕ L − ϕ M ≡ ϕ L and ϕ R − ϕ M ≡ ϕ R (here, ϕ α indicates the superconducting phase of terminal α ∈ {L, M, R} and ϕ M was set to zero by convention).This was achieved by passing currents I L and I R through two flux-bias lines, patterned on top of a uniform dielectric layer, resulting in external magnetic fluxes Φ L and Φ R respectively threading the left and right loop.Gate electrodes were deposited on the same dielectric layer and energized by voltages V α (α ∈ {S, L, M, R}) and V J , allowing for electrostatic tuning of the electron density in the InAs layer below.While terminals L and M where directly connected to the node D via Al strips, a planar JJ (named switch JJ) was integrated on terminal R. The switch JJ, with a length of 40 nm and a width of 5 µm, was designed to have a critical current much larger than that between any pairs of leads in the 4TJJ, and therefore the phase difference across the switch JJ can be neglected for the following discussion.Depending on the gate voltage V J , the switch JJ was employed in two configurations: V J = 0 (switch ON), where the JJ was conducting and Φ R could be used to control ϕ R , or V J = −1.5 V (switch OFF), where the JJ was depleted, the right loop was interrupted and terminal R was reduced to a floating superconducting island.The other gate voltages were set to V S = 0.1 V, V L = V R = −0.1 V and V M = −0.15V, unless stated otherwise.The device was measured in a dilution refrigerator with a base temperature of about 10 mK.Current-bias experiments were performed in a four-terminal configuration by driving a current I SD between S and D and measuring the voltage drop across the device, which allowed for the measurement of the switching current I sw .Along its path between S and D, the current flowed through the semiconducting region forming the four-terminal JJ, and in particular across the S-L, S-M and S-R junctions.In our geometry, the superconducting loops were designed to limit their inductance, that could in principle lead to the SDE in the system.The maximum flux variation due to the inductance of a loop, estimated to be approximately 124 pH (see details in the Supplementary Material, Section 5), for a circulating current of the order of 100 nA, is ∼ 6 × 10 −3 Φ 0 .This was observed to be negligible with respect to the flux scales over which the device properties varied.Further details regarding materials, fabrication and measurement setup are provided in the Methods section.Results on a second device, similar to the one discussed in the Main Text, are presented in the Supplementary Material (see Figs. S6-S10 in Section 4).Devices studied here were employed in a previous work that investigated hybridization of ABSs in multiterminal JJs [47].
Nonreciprocal supercurrents in the 2D phase space First, we present the differential resistance R as a function of the current bias I SD and of the left flux-line current I L for fixed right flux-line current I R = 0.1 mA.Here, R was measured with standard lock-in techniques and I SD was swept from 0 to positive or negative values to avoid retrapping effects.Figure 2a shows the result for V J = 0 (switch ON): the switching current revealed oscillations of varying amplitude as a function of I L , which, notably, were nonreciprocal at positive and negative I SD .For instance, at I L = 0.18 mA we measured switching currents I + sw = 58 nA at I SD > 0 and I − sw = 38 nA at I SD < 0 (see cyan annotations), where I ± sw > 0 by definition.This resulted in a superconducting diode efficiency η, defined as: of approximately 21%.We also note that the switching current vanished in a small range around I L ≈ −60 µA (yellow arrow), namely the device had finite differential resistance at I SD = 0. Similar maps obtained at different settings of I R are presented in Fig. S1 of the Supplementary Material.
To efficiently measure the switching currents I ± sw and the diode efficiency η as functions of both I L and I R , we changed measurement technique and periodically ramped I SD from zero to the amplitude A = ±260 nA with a repetition rate of 133 Hz, and detected when the voltage drop across the device exceeded a threshold.The time spent in the low-resistance state, averaged over 32 consecutive measurements, was converted to a current, resulting in a rapid measurement of I + sw or I − sw (depending on the sign of A) displayed in Figs.2b and 2c, respectively.A limitation of this measurement technique was that values of I sw below ∼ 10 nA could not be accurately detected due to the finite voltage threshold, which gave a finite reading of about 10 nA for small switching currents, and even when the device was resistive for zero bias current.The switching current oscillated periodically in the 2D phase space-where the periodicity axes correspond to the external magnetic fluxes Φ L and Φ R (black lines in Fig. 2b)-forming a pattern characterized by lobe-like features.The finite slope of the Φ L and Φ R axes with respect to I L and I R was due to the cross-coupling between the left (right) flux-bias line and the right (left) loop, as discussed in Section 5 of the Supplementary Material.The oscillations of I sw exhibited maxima of approximately 250 nA where Φ L and Φ R were integer multiples of the superconducting flux quantum Φ 0 = h/2e (with h the Planck constant and e the elementary charge), and minima at finite phases where the limit of detection was reached, consistent with the vanishing switching current discussed for Fig. 2a.We note that the switching currents were nonreciprocal upon reversal of the current bias, while their 2D patterns were symmetric to each other with respect to the origin (I L = I R = 0, corresponding to Φ L = Φ R = 0).The symmetry was particularly visible in the shape of the lobes, which was inverted as the supercurrent changed sign.Figure 2d shows the superconducting diode efficiency calculated from Figs. 2b and 2c using Eq. 1.As expected, η reflected the 2D periodic pattern in the phase space of the switching currents, and was widely tunable as a function of I L and I R .We observe a fully ambipolar character and large values up to η ≈ ±21% where I ± sw had a large gradient in the phase space, while the efficiency vanished in extended regions of the phase space without the need for fine tuning I L and I R .

Nonreciprocal supercurrents in single-loop configuration
Next, in Figs.2e-h we present the measurements corresponding to those discussed in Figs.2a-d but with the switch junction in the OFF state (V J = −1.5 V).From the differential resistance as a function of I SD and I L (Fig. 2e, here for I R = 17 µA), we found periodic oscillations of the switching current, with I + sw and I − sw exhibiting a phase shift from each other and opposite skewness (in the forward direction for I + sw , backward for I − sw ).Consequently, the switching currents were again nonreciprocal depending on I SD , which indicates a large JDE; at I L = 0.13 mA, for example, I + sw = 130 nA and I − sw = 68 nA (see cyan annotations), yielding η ≈ 31%.We note that, in this configuration, the switching current did not vanish for any value of I L , with minimal values of ≈ 50 nA, unlike the case with the switch ON.Measurements of I + sw and I − sw as functions of both I L and I R are shown in Figs.2f and 2g.The 2D pattern observed for V J = 0 was no longer present: as expected, the dependence on the flux Φ R was suppressed when the right superconducting loop was interrupted, and periodicity remained along a single direction.In agreement with Fig. 2e, the switching current oscillations were shifted in phase and their skewness was reversed depending on the sign of the current bias.The superconducting diode efficiency, displayed in Fig. 2h for the data of panels f and g, was also characterized by a periodic behavior as a function of Φ L and reached maxima of approximately 34%.

Gate-tunable Josephson diode effect
Electrostatic tunability over the supercurrents and the JDE was enabled by gates controlling the electron density in the semiconducting region of the 4TJJ.In Fig. 3a, we show the differential resistance as a function of the current bias (here swept from negative to positive values, thus displaying both retrapping and switching currents) while the gate voltages V L and V R varied simultaneously, for V J = 0 and I L = I R = 0.The switching current and the retrapping current, respectively 280 nA and −265 nA at V L = V R = 0, decreased for more negative voltages, until a finite resistance was measured at To investigate the voltage-tunability of the JDE, we measured the switching currents I ± sw as functions of I L and I R (as in Figs.2b,  c, f, g) for varying V L and V R , and, in each configuration, we extracted the peak values of I + sw , named I max sw , and of the superconducting diode efficiency, η max (see Supplementary Material, Section 3 for the details of the extraction procedure).The result is presented in Fig. 3b, where η max is plotted as a function of I max sw for the two settings of the switch JJ V J = 0 and V J = −1.5 V.In both cases, we observed an increasing trend of η max as I max sw increased.For any gate setting, the diode efficiency was larger at V J = −1.5 V than at V J = 0 V, up to 34% and 21% respectively (at V L = V R = 0), while I max sw was slightly smaller in the former case (up to 260 nA, instead of 280 nA for V J = 0).We further characterized the gate dependence of the device by allowing an asymmetric tuning of V L and V R (at V J = 0), as shown in Figs.4a, b and 4c, d for the configurations In each case, the switching current measured as a function of I L and I R for positive current bias is displayed in the first panel, while the second panel presents the diode efficiency extracted from I + sw and I − sw .The two configurations revealed a complementary behavior: the switching current oscillations and the diode efficiency were almost completely suppressed as a function of Φ L(R) when V L(R) was set to sufficiently negative value, depleting the semiconducting region between terminals S and L (R).This highlights the possibility of routing the supercurrents flowing in our device by gating, which enabled electrostatic control over the phase dependence of the JDE.The results obtained for V R = −0.5 V (panels a and b) were reminiscent of those previously ob-served for V J = −1.5 V (Figs. 2f-h), where data were independent of Φ R .
Finally, we restored the symmetric gate configuration V L = V R = −0.1 V and studied the effect of depleting the middle gate V M , set to −1 V (see Fig. 4e and 4f).Here, we observed periodic oscillations of the switching current along a single direction of the phase space, corresponding to the (Φ L − Φ R )-axis.The frequency of these oscillations was doubled compared to the case where V M was not depleted (e.g., Fig. 2b), consistent with the exclusion of terminal M from the current path.As a consequence, screening currents induced by the flux-bias lines only circulated in the perimeter of the double-loop geometry, leading I L and I R to control the total flux Φ L − Φ R (note that Φ L and Φ R were defined with opposite signs in Figs.1a and 1c).Notably, in this symmetric gate configuration where no current flowed into terminal M, the JDE was essentially suppressed (see Fig. 4f).Results for additional gate settings are shown in the Supplementary Material, see Figs.S2-S5.

Minimal-model description of JDE
To understand the behavior of our device in more depth, and the underlying origin of the JDE, we introduce a simple circuit model that describes the supercurrents of the 4TJJ.In the switch-ON configuration, ter- minals L, M and R are all connected to the same node D, therefore the current can flow from S to D (or from D to S) via three available JJs S-L, S-M and S-R.That is, the 4TJJ is mapped onto a bi-SQUID as three distinct JJs are connected in parallel.The total current flowing into lead S is thus expressed as: where I Sα is the current flowing from terminal S to terminal α via the corresponding JJ.First, we consider the minimal model of a single numerical parameter, schematically shown in Fig. 5a.Each of the three JJs, that are identical to each other, is described by one conductive channel with transmission τ , resulting in the CPR [49]: with ∆ the superconducting gap (∆ = 180 µeV is used considering Al leads) and ℏ = h/2π.We assume a high transmission τ = 0.9, for which the CPR of Eq. 3 has a significantly nonsinusoidal character, as harmonics higher than the first provide a sizable contribution.The independent variables in the model are the three superconducting phase differences ϕ L , ϕ R and ϕ S , defined with respect to ϕ M ≡ 0. The first two phases are related to the external magnetic fluxes by ϕ L(R) = 2πΦ L(R) /Φ 0 (neglecting the inductance of the loops, see discussion in the Supplementary Material, Section 5), whereas ϕ S varies depending on current bias I SD .The critical currents for the two bias directions are then obtained as: In Figs.5b and 5c, we show I ± c computed as functions of ϕ L and ϕ R , while the diode efficiency calculated with Eq. 1 (where I ± sw are substituted by I ± c ) is displayed in Fig. 5d.The critical currents, fulfilling the condition , exhibit patterns that are prominently asymmetric with respect to ϕ L = ϕ R = 0 (modulo 2π), which leads to a strong JDE with η up to approximately 27%.The dependence of η on ϕ L and ϕ R reflects the triangular shapes observed for I ± c , with features arranged according to three main orientations in the phase space.The origin of the JDE is investigated by fixing ϕ L and ϕ R and computing the CPR of Eq. 2 as a function of ϕ S , I S (ϕ S ), and its components I SL (ϕ S ), I SM (ϕ S ) and I SR (ϕ S ), all obtained from Eq. 3.
For simplicity we always keep ϕ R = 0 and select four values of ϕ L (colored markers in Fig. 5d), where |η| is either zero (ϕ L = 0, π) or maximal (ϕ L = 0.78π, 1.22π).The individual and combined CPRs at these phase-space points are plotted in Fig. 5e-h.In each case, we identify the values of ϕ S that maximize the total current I S (ϕ + S , red dotted lines) and its inverse −I S (ϕ − S , green dotted lines), such that I S (ϕ ± S ) = I ± c .The currents flowing to and from terminal S are schematically depicted in Fig. 5i-l for the same ϕ L and ϕ R values of panels eh.In the schematics, red (green) arrows show the situation at ϕ , their width and direction indicate the magnitude and direction of the current.We note that all individual CPRs I Sα (ϕ S ) have the same amplitude ≈ 30 nA and skewness, both given by the transmission τ (identical for the three channels), but notably I SL (ϕ S ) is phase-shifted by ϕ L .When ϕ L = 0 (Fig. 5e, i), all components are in-phase and I S (ϕ S ) = 3I Sα (ϕ S ), hence a standard nonsinusoidal CPR is obtained.Positive and negative critical currents are identical, and all currents are simply reversed between ϕ + S and ϕ − S .In contrast, when I SL (ϕ S ) is shifted by ϕ L = 0.78π (Fig. 5f, j), the total CPR becomes nonreciprocal for positive and negative currents.The I SL -component is very small at ϕ + S , but comparable with I SM,SR at ϕ − S ; since in both cases I SL has opposite sign with respect to I SM,SR , this asymmetry leads to I + c > I − c .A symmetric scenario is recovered for ϕ L = π, when I SL is shifted by half period from the other components.Here, I S always has the opposite sign to I SM,SR , but same absolute value at ϕ ± S , such that I + c = I − c and no JDE is present.Finally, the results obtained for ϕ L = 1.22π (Fig. 5h,l), symmetric about ϕ L = π to ϕ L = 0.78π, show the same CPRs discussed for Fig. 5f,j upon sign inversion of both current and ϕ S , confirming that here the JDE is strong and has opposite direction compared to the previous case.
We note that the JDE has been derived within our minimal model despite the presence of three identical channels, i.e., of same harmonic content, whereas in a conven-tional SQUID comprising two JJs the harmonic content must be different between the two JJs [29].The multiterminal geometry that we discuss can also be reduced to a conventional SQUID, where two JJs and a phase degree of freedom (for example, the S-M and S-R junctions and ϕ R ) are replaced by an effective JJ of tunable harmonic content.The effective JJ, together with the third JJ and the remaining phase difference (in the same example, S-L and ϕ L ), realizes the proposal of Ref. [29].An important advantage offered by our platform lies in the possibility of phase-tuning the harmonic content of the effective junction, establishing wide and flexible control over the JDE.The nonsinusoidal character of the individual CPRs, which is still a requirement, is obtained in high-transmission hybrid JJs (as those realized in this work), while our novel geometry eliminates the need for precise control over the transmissions of the single junctions after device fabrication.

Simulations with the extended model
After discussing the origin of the JDE by means of a minimal, single-parameter model, we extend the latter to better capture the experimental data presented in Fig. 2. Again, we consider the three JJs S-L, S-M and S-R that contribute to the total current according to Eq. 2. For each junction we consider two contributions to the current I Sα : in addition to a high-transparency channel, with transmission τ α , a component with conventional sinusoidal CPR [50], associated to a large number of low-transmission channels, is included: where e∆T α /2ℏ is the critical current of the sinusoidal component and T α the sum of the transmissions of all low-transmission channels.We note that τ α and T α may vary depending on the junction S-α.With this extended model, that is schematically represented in Fig. 6a, we compute the critical currents using Eq. 4 for any settings of ϕ L and ϕ R .The simulated I + c , I − c and η are shown in Fig. 6b-d for parameters τ L = τ R = 0.92, τ M = 0.89, T L = 3.5, T M = 1.5 and T R = 3.6.For a better comparison to the experimental results, the three quantities are plotted as functions of the flux-bias line currents I L and I R , calculated from the phases ϕ L and ϕ R by applying a linear transformation (see Supplementary Material, Section 5 for more details).Simulations reproduced the measurements displayed in Fig. 2b-d to a good degree.Calculated critical currents were between 10 and 270 nA, with diode efficiencies up to η max ≈ 25% and patterns in the 2D phase space closely resembling the experimental data.By comparing the simulation of η in Fig. 6d to the result previously obtained with the minimal model (Fig. 5d), we note a reduction of |η| and broadening of the features located near (ϕ L , ϕ R ) = (π, π), modulo 2π (see black arrows in both figures).This effect, also clearly visible in Fig. 2d, is mainly related to the sinusoidal components to the CPR of Eq. 5, where T M is substantially smaller than T L,R , and marginally related to τ M , only slightly smaller than τ L,R .This is expected in the device under study, as the larger length of the S-M JJ (lithographically of 120 nm) compared to S-L and S-R (50 nm) reduced both the transmission of the most transmissive modes and the number of channels with low transmission.
The switch-OFF configuration (Fig. 2e-h) is investigated by further adjusting the numerical model based on the following considerations.When the right superconducting loop is interrupted, the current flowing from terminal S to R does not have a direct path to D, but it must flow across the R-M junction.Thus, we introduce this junction in the model, with CPR I RM also assumed to have the form of Eq. 5.Here the phase difference ϕ R − ϕ M = ϕ R is used instead of ϕ S − ϕ α and parameters τ RM and T RM substitute τ α and T α (see schematic of Fig. 6e).For these parameters we choose the values τ RM = 0.97 and T RM = 3.2.The other consequence of interrupting the right loop is that ϕ R is not controlled externally with a magnetic flux, hence it is first calculated imposing the condition I SR (ϕ S − ϕ R ) = I RM (ϕ R ) (i.e., the current flowing from S to R equals that flowing from R to M), for any value of ϕ S .Once ϕ R is determined, I ± c (ϕ L ) is computed using Eqs.2, 4 and 5, leading to the result shown in Figs.6f and 6g.In agreement with Figs.2f and 2g, the model produces oscillations of I ± c as a function of ϕ L between 50 nA and 240 nA, with a phase shift when reversing the current direction.This results in a diode efficiency (see Fig. 6h) up to 40%, comparable to the measured value of ≈ 34% and exhibiting an oscillating behavior depending on ϕ L , similar to that in Fig. 2h.
The higher η obtained in the switch-OFF case is understood by considering the higher asymmetry in the supercurrent distribution obtained in this setting.In fact, the supercurrent flowed directly from S to the common node D only via S-L and S-M, which had largely different transmissions due to the device geometry, while it had to traverse both S-R and R-M to reach D via R.This realized a strongly asymmetric situation, where junctions with different harmonic components led to large diode efficiencies [29].When the switch was ON (Figs. 2d and 6d) and junction S-R directly connected S to D, the supercurrent distribution became more symmetric, and spatial-inversion symmetry was broken by the different phases tuned with the loops: that is, local magnetic fluxes broke both time-reversal and spatial-inversion symmetry.Similar arguments apply to the case of Figs.4b and 4d, however setting gates to negative values to deplete parts of the semiconducting region reduced the maximum switching current, which also resulted in a decrease of the JDE efficiency (see Fig. 3).The absence of JDE for the situation of Fig. 4f is explained by considering that, with terminal M blocked, the supercurrent flowed in S-L and S-R only, which were almost balanced channels.Furthermore, phase tuning could not break spatial-inversion symmetry with M blocked, effectively resulting in a single superconducting loop between L and R.This situation therefore realized the balanced SQUID device of Ref. [29], showing no JDE despite the nonsinusoidal CPR of the individual junctions.
We finally note that our model captured the main experimental results well without invoking hybridized ABSs in the semiconducting region, even though such states were measured in the same devices by means of local tunneling spectroscopy [47].There, the terminal S was weakly coupled to the multiterminal region and ABSs arising in the L-M and M-R junctions overlapped.In the present case, these JJs were not required to describe the experimental data (except for the switch-OFF configuration, where the M-R junction was not phasecontrollable), since the supercurrents flowing from S to L, M and R had direct superconducting paths to D, without traversing L-M or M-R; this also excluded the contribution of hybridized modes between the two JJs.Furthermore, supercurrents were transported by several ABSs present in our devices, most of which solely depended on phase differences between pairs of superconducting contacts.Presumably, there were very few hybridized ABSs and they were localized close to the center of the multiterminal region.Thus, in the geometry studied here, they did not provide a significant contribution to the total supercurrent.

CONCLUSIONS
We reported switching current measurement of a 4TJJ in a InAs/Al heterostructure hosting ABSs with large transmission probabilities, resulting in nonsinusoidal CPRs between pairs of terminals.The switching current measured between two contacts showed a strong dependence on the bias current direction, resulting in a JDE.The JDE efficiency could be widely controlledboth in amplitude and sign-by magnetic fluxes, independently tuned via integrated flux-bias lines, and gate electrodes, which routed the supercurrent to different transport channels.No external magnetic fields were required.In a first gate setting, where transport through the entire semiconductor region was allowed, the JDE efficiency was periodically modulated by magnetic fluxes, with peak values reaching η ≈ ±21%, including large regions in parameter space with η ≈ 0. When a superconducting arm was interrupted, introducing a larger asymmetry in the supercurrent distribution, a peak efficiency η ≈ ±34% was reached.The 4TJJ was mapped onto a simple bi-SQUID geometry, with three parallel JJs containing ABSs with large transmission probability.A theoretical model reproduced the experimental observations to a good degree, including switching current and diode efficiency patterns.In our devices, the JDE is a consequence of the nonsinusoidal CPR and the multiterminal geometry, which allows breaking of spatialinversion symmetry by controlling the magnetic fluxes in the loops.Unlike realizations based on a single loop, an asymmetry between junctions is not required.Our work highlights the potential of phase-tunable multiterminal JJs to engineer JDE with large and widely controllable efficiencies, without the need for exotic materials or external magnetic fields, and underscores the role of these devices as a versatile platform for upcoming applications.

Materials and Fabrication
Devices were realized in a III-V heterostructure grown by molecular beam epitaxy on an InP (001) substrate [46].The semiconducting stack (starting from the substrate) consisted of a 1100 nm thick step-graded InAlAs buffer layer, a 6 nm thick In 0.75 Ga 0.25 As layer, an 8 nm thick InAs layer, a 13 nm thick In 0.75 Ga 0.25 As layer and two monolayers of GaAs.On top, an epitaxial 15 nm thick Al layer was deposited in situ without breaking vacuum.A two-dimensional electron gas (2DEG) was confined in the InAs and its properties were characterized via measurements performed in a Hall bar geometry, which gave an electron peak mobility of 18000 cm 2 V −1 s −1 at an electron sheet density of 8 × 10 11 cm −2 .This resulted in an electron mean free path l e ≳ 260 nm and a superconducting coherence length of the 2DEG proximitized by the Al sheet of ξ InAs = ℏv F l e / (π∆) ∼ 600 nm, with v F the Fermi velocity in the 2DEG and ∆ the induced superconducting gap.
In the fabrication process, large mesa structures were first isolated, suppressing parallel conduction between devices and across the middle regions of the superconducting loops.This was done by selectively etching the Al layer with Transene type D, followed by a second chemical etch to a depth of ∼ 380 nm into the III-V material stack, using a 220 : 55 : 3 : Next, features were defined in the Al layer by wet etching with Transene type D at 50 • C for 4 s.The dielectric, uniformly deposited on the entire chip by atomic layer deposition, consisted of a 3 nm thick layer of Al 2 O 3 and a 15 nm thick layer of HfO 2 .Gate electrodes and flux-bias lines were defined by evaporation and lift-off.In a first step, 5 nm of Ti and 20 nm of Au were deposited to realize the fine features of the gates; in a second step, a stack of Ti/Al/Ti/Au with thicknesses 5 nm, 340 nm, 5 nm and 100 nm was deposited to connect the mesa structure to the bonding pads and to define the flux-bias lines.

Measurements Techniques
Experiments were performed in a dilution refrigerator with a base temperature at the mixing chamber below 10 mK.The sample was mounted on a QDevil QBoard sample holder system, without employing any light-tight enclosure.Electrical contacts to the devices, excepts for the flux-bias lines, were provided via a resistive loom with QDevil RF and RC low-pass filters at the mixing chamber stage, and RC low-pass filters integrated on the QBoard sample holder.Currents were passed through the fluxbias lines via a superconducting loom with only QDevil RF filters at the mixing chamber stage.Signals were applied to all gates and flux-bias lines via home-made RC filters at room temperature.
In all electrical measurements, a bias current I SD was driven between terminal S and node D of the device by applying equal and opposite voltages to S and D via bias resistors, whose resistance was much larger than that of the device under study.The voltage drop across S and D was detected in a four-terminal configuration.Measurements of the differential resistance were performed with lock-in-amplifier techniques, by applying a fixed AC current δI = 2.5 nA to D in addition to the DC bias I SD and detecting the AC voltage δV between S and D, thus obtaining the differential resistance R ≡ δV /δI.Measurements of I ± sw were done by periodically ramping I SD from 0 to an amplitude A, where A was positive or negative depending on whether I + sw or I − sw was measured; the absolute value of A was adjusted depending on the gate configuration to be slightly larger than I ± sw .The signal form was a sawtooth wave, applied at a frequency f = 133 Hz using a waveform generator.The voltage drop across S and D was measured with an oscilloscope (averaging 32 measurements), which detected the time interval ∆t where the voltage was below a threshold, hence allowing for the calculation of the switching current as I ± sw = |A|f ∆t.The dilution refrigerator was equipped with a superconducting vector magnet which, despite not being utilized for the experiments, produced a small magnetic field offset.Therefore, small offsets in the flux-bias line currents I L and I R (up to ∼ 100 µA) were considered in datasets, in such a manner that the point where I L = I R = 0 corresponded to a point of the phase space where η = 0 and I ± sw were maximal, as expected when no magnetic fluxes thread the superconducting loops.
[51] Geometric inductance Lgeom of a loop was calculated analytically using the following expression, valid for a rectangular loop:  The results shown thus far were acquired with symmetric gate voltages V L = V R , except in Fig. 4a-d of the Main Text where either gate was strongly depleted.In these configurations, the currents flowing into terminals L and R were relatively symmetric, as supported by our simulations (Fig. 6), where a good fit was found for τ L = τ R and T L ≈ T R .For V L = V R = −0.3V, we observed switching current patterns that were slightly asymmetric along the two periodicity directions, as shown in Figs.S.3a and S.3b (see cyan arrows in panel a).This was likely due to different lever arm of the gates at voltages V L and V R , which created an imbalance in the device for intermediate gate voltages.By setting V L = −0.28V and V R = −0.31V, a more balanced situation was restored (see Figs. S.3d and S.3e).This effect was also visible in the superconducting diode efficiencies, shown in Figs.S.3c and S.3f for the two cases: while the maximum |η| slightly varied depending on the periodicity axis at V L = V R = −0.3V, it was substantially more symmetric in the two directions at V L = −0.28V, V R = −0.31V (see black arrows in panels c and f, respectively).
Staying in the gate configuration with V L = −0.28V, V R = −0.31V, we defined two phase-space linecuts (colored markers in

EXTRACTING THE DIODE EFFICIENCY AS A FUNCTION OF VL, VR
In Fig. 3b of the Main Text, we showed the gate-tunability of the JDE in our devices by presenting the dependence of the maximum diode efficiency η max as a function of the gate voltages V L = V R .In the switch-ON configuration (V J = 0), each data point was extracted from measurements of I + sw and I − sw taken as a function of both I L and I R .Figures S.5a-e and S.5f-j display I + sw and η obtained using Eq. 1 of the Main Text for five selected gate configurations ranging between V L = V R = −0.3V and V L = V R = 0. Since values close to the limit of detection (∼ 10 nA) gave large variability of the extracted η (see for example Figs.S.3c and S.3f in the regions of phase space where I + sw was ≳ 10 nA), regions where I + sw was lower than a threshold of 20 nA were not considered.We note that the exact choice of the threshold did not significantly alter the result of the extraction.In each gate configuration, I max sw and η max were obtained by considering the 99.9th percentile of I + sw and η, respectively, throughout the corresponding maps.In switch-OFF case (V J = −1.5 V), included in Fig. 3b of the Main Text, the extraction was simplified for two reasons: first, since only one periodicity axis remained in the phase space, I ± sw could be measured along a single direction (e.g., as a function of I L for any fixed I R ), thus improving both speed and resolution of the measurement; second, I ± sw did not approach the limit of detection very closely, therefore a threshold was not required to select the data.Similar to the switch-ON case, I max sw and η max were obtained by considering the 99.9 percentile of I + sw and η for each gate setting.

RESULTS FOR DEVICE 2
To further study the JDE arising in a four-terminal Josephson junction (4TJJ) embedded in a double-loop geometry, we characterized a second device fabricated on the same chip.The circuit layout of Device 2 and the geometry of the two superconducting loops were lithographically identical to Device 1 (see Figs. 1a and 1c of the Main Text).The 4TJJ region, displayed in Fig. S.6, featured a different layout of terminal S (significantly wider than for Device 1), whereas terminals L, M and R were designed to be identical between the two devices.The shape of the gates was also varied, in particular for the gate energized by the voltage V S .
Current-bias measurements were performed as described for Device 1. Figure S.7 shows the switching current I ± sw and the extracted diode efficiency η as functions of the flux-line currents I L and I R for three configurations of the gate voltages V L and V R (set to a common value): −0.4 V (a-c), −0.5 V (d-f) and −0.6 V (g-i).The other gate voltages were V S = 0.15 V, V M = −0.15V and V J = 0 (switch ON).Switching current oscillations in the 2D phase space at V L = V R = −0.4V qualitatively resemble those observed for Device 1 in Figs.2b and 2c of the Main Text.The larger current maxima and minima, occurring despite voltages were applied in a more negative range than in Device 1, are understood by considering the different geometry of terminal S, that is compatible with a higher number of conduction channels in the S-L and S-R junctions, and a stronger screening of the electric field generated by the gates.Another feature of Device 2, that was particularly visible at V L = V R = −0.5 V, − 0.6 V, was the large asymmetry between the two periodicity directions Φ L and Φ R .This is attributed to a smaller supercurrent flowing from S to L than from S to R, likely due to a combination of a smaller number and transmission of the modes on the left side of the device, even for symmetrically applied gate voltages.We note that the case with V L = V R = −0.6V is qualitatively similar to Figs. 4c and 4d of the Main Text, where only V L was depleted.The asymmetry was reflected in the diode efficiency η: while oscillations of η in the phase space had some resemblance with those of Device 1 (see Figs. 2d of the Main Text), and also reached large maxima up to |η| ≈ 28%, they showed different amplitude and features depending on which flux was varied.A prominent example is visible in Fig. S.7c, where features of η near the phase-space points (Φ L , Φ R ) = (0, Φ 0 /2) (modulo Φ 0 ), marked by the orange arrow, have different shape and smaller η than those near (Φ L , Φ R ) = (Φ 0 /2, 0) (purple arrow).Conversely, for V L = V R = −0.5 V, − 0.6 V, η was larger in proximity (Φ L , Φ R ) = (0, Φ 0 /2), consistent with the earlier suppression of Φ L dependence as the gate voltages were lowered.
Switching currents and diode efficiency of Device 2 were also measured in the switch-OFF configuration (V J = −1.5 V), as shown in The results shown for Device 2 were qualitatively captured by our extended theoretical model, with parameters (τ L , τ M , τ R , T L , T M , T R ) set to (0.91, 0.87, 0.93, 3.5, 2, 6.5) for Figs.S.9a-c (Configuration 1), to (0.44, 0.65, 0.87, 1, 1, 3.3) for Figs.S.9d-f (Configuration 2), and to (0, 0.53, 0.67, 0.2, 0.2, 1) for Figs.S.9g-i (Configuration 3).Furthermore, we simulated the device in the switch-OFF case using the same parameters as in Configuration 2 and, in addition, τ RM = 0.75, T RM = 4; the result is displayed in Fig. S.10.In all cases, the phase axes (ϕ L , ϕ R ) were converted to flux-line-current axes (I L , I R ) using the transformation described in Section 5. We note that the chosen parameters were such that τ L < τ R and T L < T R , supporting our interpretation of the asymmetry between Φ L and Φ R as a result of asymmetric supercurrent flow in the device between terminals L and R. In Configuration 3, the data was best described by using τ L = 0, suggesting that the high-transmission channel between S and L was depleted.The measurements performed on Device 2 and the simulations done within the same model introduced for Device 1 support the generality of the observed phenomena, and in particular corroborate the presence and origin of the JDE in our device.

CURRENT-TO-FLUX REMAPPING
The b-SQUID geometry of our devices enables control over two superconducting phase differences (between terminals L and M, and between R and M), tuned by the currents in the two flux-bias lines, I L and I R .These currents generated magnetic fluxes threading the two superconducting loops, Φ L and Φ R , with a cross-coupling leading to an effect of I L(R) on the flux through the opposite loop, Φ R(L) .As a consequence, the Φ L -and Φ R -axes had a finite slope with respect to the I L -and I R -axes, as visible in Fig. 2b of the Main Text.We describe the cross-coupling by considering a mutual inductance matrix M that relates flux Φ L and Φ R to flux-line currents I L and I R : To quantify M (for Device 1), we consider the (Φ L , Φ R ) and (I L , I R ) coordinates of two points of the phase space [in addition to the origin, (Φ L , Φ R ) = (I L , I R ) = (0, 0)], such as (Φ 0 , 0) and (0, Φ 0 ), and substitute them in Eq. 6 [47].
The resulting 4 × 4 equation system leads to the mutual inductance matrix: The inverse transformation, obtained by inverting the mutual inductance matrix, was employed to map the phase space (ϕ L , ϕ R ) to the flux-line-current space (I L , I R ) for the simulated data of Figs. 6 of the Main Text, S.9 and S.10.In this transformation, the phase differences were considered to be linearly related to the fluxes, thus Φ L(R) = Φ 0 × ϕ L(R) /2π were substituted in Eq. 6 to obtain a direct relation between phases and currents.This assumption is justified by noting that the inductance of the superconducting loops, comprising geometric and kinetic contributions L loop = L geom + L k , is negligible compared to the Josephson inductance L J existing between any pairs of terminals in the 4TJJ.For each superconducting loop, the geometric inductance is estimated as L geom ≈ 24 pH [51], while the kinetic inductance is calculated using the expression [52]: where l = 57 µm is the length of the loop perimeter, w = 1 µm the width of the Al strip forming the loop, h the Planck's constant, R □ ≈ 1.5 Ω the normal state resistivity of the heterostructure stack (measured in Hall bar geometry where the Al was not removed) and ∆ ≈ 180 µeV is the superconducting gap of Al.Geometric and kinetic contributions lead to a total inductance L loop ≈ 124 pH.The Josephson inductance between two superconducting terminals (for example, L and M when considering the left loop) is estimated as L J = Φ 0 /2πI c ∼ 3 nH, where I c ∼ 100 nA gives the order of magnitude of the junction's critical current.

FIG. 1 .
FIG. 1. Device under study and measurement setup.(a) False-colored scanning electron micrograph of a device identical to that under study.Exposed III-V semiconductor is represented in pink, Al in blue, gate electrodes in yellow and flux-bias lines in purple.Bias current ISD, flux-line currents IL and IR, magnetic fluxes threading the superconducting loops ΦL and ΦR, and gate voltages VS, VL, VM, VR and VJ are labeled.Superconducting terminals S, L, M, R and the common node D are also indicated.(b) Zoom-in of (a) in the vicinity of the four-terminal Josephson junction.(c) Schematic representation of the device with the measurement setup, using the same color labeling as in (a) and (b).Gate electrodes are not shown.

FIG. 2 .
FIG. 2. Phase-tunable Josephson diode effect.(a) Differential resistance R as a function of left flux-line current IL and source-drain bias current ISD, for fixed right flux-line current IR = 0.1 mA.The map is obtained by merging two datasets recorded with ISD ramping from 0 to either positive or negative values (see white arrows).Switching current nonreciprocities are highlighted by cyan annotations.A point where the switching current reaches zero is indicated by the yellow arrow.Gate voltages were set to VL = VR = −0.1 V, VS = 0.1 V, VM = −0.15V and VJ = 0. (b, c) Switching currents I + sw and I − sw , measured for positive and negative ISD respectively, as functions of IL and IR.Arrows in (b) indicate the directions along which magnetic fluxes threading the left and right superconducting loop, ΦL and ΦR, vary independently.Each arrow represents the addition of one superconducting flux quantum Φ0 to the corresponding flux.(d) Superconducting diode efficiency η calculated from (b) and (c) using Eq. 1 (see text), as a function of IL and IR.(e-h) As in (a-d), but measured for VJ = −1.5 V, which sets the switch JJ to the OFF state and interrupts the right loop.

FIG. 3 .
FIG. 3. Gate-tuning of the maximum switching current and diode efficiency.(a) Differential resistance R as a function of gate voltages VL = VR and bias current ISD (swept from negative to positive values, see white arrow).(b) Maximum Josephson diode efficiency η max as a function of the maximum switching current I max sw for multiple values of VL = VR (see colorscale).Each point is obtained from maps similar to Figs. 2b and 2c (see Supplementary Material, Section 3 for more details).Full circles refer to the situation with VJ = 0, empty diamonds to the situation with VJ = −1.5 V.

FIG. 4 .
FIG. 4. Routing of the supercurrent.(a) Switching current I + sw measured for positive bias current ISD, as a function of fluxline currents IL and IR.Measurements are performed with VL = −0.1 V and VR = −0.5 V. (b) Diode efficiency η for the configuration of (a).(c, d) As in (a, b), but for VL = −0.5 V and VR = −0.1 V. (e, f) As in (a, b), but for VL = −0.1 V, VR = −0.1 V, and VM = −1 V.

FIG. 5 .
FIG. 5. Minimal-model description of the Josephson diode effect.(a) Schematic representation of the four-terminal Josephson junction and circuit parameters.(b, c) Simulated critical currents I + c and I − c for positive and negative ISD, respectively, as functions of the phase differences ϕL and ϕR.The transmission of the three channels is τ = 0.9.(d) Diode efficiency η derived from (b) and (c) as a function of ϕL and ϕR.(e-h) Supercurrents in the four leads as functions of phase ϕS.The phases of the other leads are indicated in each panel.The four cases correspond to the colored markers in (d).The value of ϕS where IS has its maximum I + c (minimum I − c ), labeled ϕ + S (ϕ − S ), is highlighted by the red (green) dotted line.(i-l) Schematic representation of the supercurrent flow in the phase configurations shown in (e-h).Red and green arrows indicate supercurrents for ϕ + S and ϕ − S , respectively.The wider the arrow, the larger the supercurrent.

FIG. 6 .
FIG. 6. Josephson diode effect in the extended model.(a) Schematic representation of the four-terminal Josephson junction and circuit parameters for the switch-ON configuration (see text for details).(b, c) Simulated critical currents I + c and I − c for positive and negative current bias (respectively), as functions of the flux-line currents IL and IR.Currents IL and IR are calculated from the superconducting phase differences ϕL, ϕR and the mutual inductance matrix (see discussion in the Supplementary Material, Section 5).Black arrows, whose directions indicate the periodicity axes ϕL and ϕR, represent the corresponding phase winding by 2π.(d) Diode efficiency η obtained from (b) and (c) as a function of IL and IR.(e) Schematic representation of the four-terminal Josephson junction and circuit parameters for the switch-OFF configuration.(f, g) As in (b, c), but for the case with switch-OFF.(h) Diode efficiency η obtained from (f) and (g) as a function of IL and IR.

Figures S.
Figures S.2a-c show three phase-space linecuts, indicated by the colored markers in Fig. S.1a, where the gate voltages V L and V R were set to −0.2 V (while V L = V R = −0.1 V in Fig. 2 of the Main Text and in Fig. S.1).The other gate voltages were kept to V S = 0.1 V, V M = −0.15V and V J = 0.The switching current oscillations qualitatively resembled those described for V L = V R = −0.1 V (Fig. S.1) but with reduced amplitude, as the maximum switching current was approximately 170 nA in agreement with Fig. 3b of the Main Text.Regions of vanishing supercurrent (see for example the yellow arrow in Fig. S.2a) were more prominent in this gate configuration, consistent with the larger normal-state resistance.The linecut of Fig. S.2b (I R = 20 µA) was also measured with the switch junction voltage set to V J = −1.5 V (switch OFF, Fig. S.2d), yielding a picture very similar to Fig. 2e of the Main Text.With respect to the case where V L = V R = −0.1 V, we confirm a reduction of the maximum supercurrent (up to about 170 nA) and diode efficiency (up to approximately 25%).The results shown thus far were acquired with symmetric gate voltages V L = V R , except in Fig.4a-d of the Main Text where either gate was strongly depleted.In these configurations, the currents flowing into terminals L and R were relatively symmetric, as supported by our simulations (Fig.6), where a good fit was found for τ L = τ R and T L ≈ T R .For V L = V R = −0.3V, we observed switching current patterns that were slightly asymmetric along the two periodicity directions, as shown in Figs.S.3a and S.3b (see cyan arrows in panel a).This was likely due to different lever arm of the gates at voltages V L and V R , which created an imbalance in the device for intermediate gate voltages.By setting V L = −0.28V and V R = −0.31V, a more balanced situation was restored (see Figs. S.3d and S.3e).This effect was also visible in the superconducting diode efficiencies, shown in Figs.S.3c and S.3f for the two cases: while the maximum |η| slightly varied depending on the periodicity axis at V L = V R = −0.3V, it was substantially more symmetric in the two directions at V L = −0.28V, V R = −0.31V (see black arrows in panels c and f, respectively).Staying in the gate configuration with V L = −0.28V, V R = −0.31V, we defined two phase-space linecuts (colored markers in Fig. S.3d, corresponding to I R = 20 µA and I R = −140 µA) and measured R along these directions as a function of I L and I SD .The result is presented in Figs.S.4a and S.4b, showing switching current oscillations with maxima of about 70 nA and minima where the supercurrent vanished.Nonreciprocity was still present in the switching current depending on the sign of I SD , despite less markedly than for the previous gate configurations (where V L and V R were set to less negative values), consistent with diode efficiencies up to approximately 10% reported in Fig. S.3f.Finally, the gate voltage V J was set to −1.5 V to operate with the switch OFF, and supercurrent oscillations were measured along the linecut at I R = 20 µA (see Fig. S.4c), also revealing maximum switching currents of close to 70 nA.
Figures S.2a-c show three phase-space linecuts, indicated by the colored markers in Fig. S.1a, where the gate voltages V L and V R were set to −0.2 V (while V L = V R = −0.1 V in Fig. 2 of the Main Text and in Fig. S.1).The other gate voltages were kept to V S = 0.1 V, V M = −0.15V and V J = 0.The switching current oscillations qualitatively resembled those described for V L = V R = −0.1 V (Fig. S.1) but with reduced amplitude, as the maximum switching current was approximately 170 nA in agreement with Fig. 3b of the Main Text.Regions of vanishing supercurrent (see for example the yellow arrow in Fig. S.2a) were more prominent in this gate configuration, consistent with the larger normal-state resistance.The linecut of Fig. S.2b (I R = 20 µA) was also measured with the switch junction voltage set to V J = −1.5 V (switch OFF, Fig. S.2d), yielding a picture very similar to Fig. 2e of the Main Text.With respect to the case where V L = V R = −0.1 V, we confirm a reduction of the maximum supercurrent (up to about 170 nA) and diode efficiency (up to approximately 25%).The results shown thus far were acquired with symmetric gate voltages V L = V R , except in Fig.4a-d of the Main Text where either gate was strongly depleted.In these configurations, the currents flowing into terminals L and R were relatively symmetric, as supported by our simulations (Fig.6), where a good fit was found for τ L = τ R and T L ≈ T R .For V L = V R = −0.3V, we observed switching current patterns that were slightly asymmetric along the two periodicity directions, as shown in Figs.S.3a and S.3b (see cyan arrows in panel a).This was likely due to different lever arm of the gates at voltages V L and V R , which created an imbalance in the device for intermediate gate voltages.By setting V L = −0.28V and V R = −0.31V, a more balanced situation was restored (see Figs. S.3d and S.3e).This effect was also visible in the superconducting diode efficiencies, shown in Figs.S.3c and S.3f for the two cases: while the maximum |η| slightly varied depending on the periodicity axis at V L = V R = −0.3V, it was substantially more symmetric in the two directions at V L = −0.28V, V R = −0.31V (see black arrows in panels c and f, respectively).Staying in the gate configuration with V L = −0.28V, V R = −0.31V, we defined two phase-space linecuts (colored markers in Fig. S.3d, corresponding to I R = 20 µA and I R = −140 µA) and measured R along these directions as a function of I L and I SD .The result is presented in Figs.S.4a and S.4b, showing switching current oscillations with maxima of about 70 nA and minima where the supercurrent vanished.Nonreciprocity was still present in the switching current depending on the sign of I SD , despite less markedly than for the previous gate configurations (where V L and V R were set to less negative values), consistent with diode efficiencies up to approximately 10% reported in Fig. S.3f.Finally, the gate voltage V J was set to −1.5 V to operate with the switch OFF, and supercurrent oscillations were measured along the linecut at I R = 20 µA (see Fig. S.4c), also revealing maximum switching currents of close to 70 nA.
Fig. S.8 for V L = V R = −0.5 V. Oscillations of both I ± sw and η, suppressed along Φ R , were similar to those reported for Device 1 in Figs.2f-h of the Main Text.Interestingly, the maximum diode efficiencies of approximately 12% were significantly lower than in the corresponding switch-ON case (Fig. S.7f), where η max ≈ 25%.Again, this is attributed to the asymmetric supercurrent distribution in Device 2, which led to small diode efficiencies along the Φ L -axis and required tuning of Φ R to reach larger values in the case of Fig. S.7f .When the switch was OFF, control over Φ R was disabled, hence reducing η max .
pH −1.39 pH −1.67 pH 5.80 pH for Device 2. We note that M is very similar between the two devices, as the loop and flux-line geometry was lithographically identical.In Fig. S.11, we apply M from Eq. 7 to perform a basis transformation and plot the data presented in Figs.2b-d (shown again in Figs.S.11a-c) as a function of the magnetic fluxes Φ L and Φ R (see Fig. S.11d-f).

FIG. S. 1 .
FIG. S.1.Phase-space linecuts at VL = VR = −0.1 V. (a) Switching current I + sw , measured for ISD > 0, as a function of flux-line currents IL and IR, as in Fig. 2b of the Main Text.Colored markers indicate the position of IR = 100 µA (green), IR = 20 µA (white) and IR = −60 µA (blue).(b-d) Differential resistance R as a function of IL and ISD for IR = 100 µA (b), IR = 20 µA (c) and IR = −60 µA (d), as indicated in (a).Each map is obtained by merging two datasets recorded with ISD ramping from 0 to either positive or negative values [see white arrows in (b)].

FIG. S. 5 .
FIG. S.5.Results for varying VL, VR and extraction of diode efficiencies.(a-e) Switching current I + sw , measured for ISD > 0, as a function of flux-line currents IL and IR for five settings of VL = VR, indicated on the subfigures.(f-j) Diode efficiency extracted from (a-e) and the corresponding measurements of I − sw (not shown), respectively, as a function of IL and IR.The other gate voltages were kept to VS = 0.1 V, VM = −0.15V and VJ = 0.

FIG. S. 9 .
FIG. S.9.Simulations with the extended model for Device 2. (a, b) Critical currents I + c and I − c , simulated for positive and negative current bias (respectively), as functions of flux-line currents IL and IR, using the parameters of Configuration 1 (see text).The model is described in the Main Text.Currents IL and IR were obtained from the superconducting phase differences ϕL (between terminals S and L) and ϕR (between S and R) by applying a linear transformation (see Section 5 for additional details).Phase axes ϕL and ϕR, that are the periodicity directions, are indicated by the black arrows, whose length represents winding of the corresponding phase by 2π.(c) Diode efficiency η extracted from (a) and (b) as a function of IL and IR.(d-f) As in (a-c), but using the parameters of Configuration 2. (g-i) As in (a-c), but using the parameters of Configuration 3.